S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 521
S912XEQ512J3CAGR
Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XEQ512J3CAGR
Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Available stocks
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Part Number:
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13.3.2.10 ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
13.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x000C
Module Base + 0x000E
CMPHT[15:0]
IEN[15:0]
Reset
Reset
Field
15–0
Field
15–0
W
W
R
R
15
15
0
0
ATD Digital Input Enable on channel x (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls
the digital input buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
Compare Operation Higher Than Enable for conversion number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5,
4, 3, 2, 1, 0) of a Sequence — This bit selects the operator for comparison of conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
14
14
0
0
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
Figure 13-13. ATD Compare Higher Than Register (ATDCMPHT)
13
13
0
0
Figure 13-12. ATD Input Enable Register (ATDDIEN)
12
12
0
0
Table 13-21. ATDCMPHT Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-20. ATDDIEN Field Descriptions
11
11
0
0
10
10
0
0
0
0
9
9
CMPHT[15:0]
IEN[15:0]
0
0
8
8
Description
Description
0
0
7
7
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0
521
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