S912XEQ512J3CAGR Freescale Semiconductor, S912XEQ512J3CAGR Datasheet - Page 92
S912XEQ512J3CAGR
Manufacturer Part Number
S912XEQ512J3CAGR
Description
16-bit Microcontrollers - MCU 16 BIT,512K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XEQ512J3CAGR
Rohs
yes
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 kB
Data Ram Size
32 kB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
Interface Type
CAN/SCI/SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEQ512J3CAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 2 Port Integration Module (S12XEPIMV1)
92
Port
E
K
Pin Name
PK[6:4]
PK[3:0]
PE[7]
PE[6]
PE[5]
PE[4]
PE[3]
PE[2]
PE[1]
PE[0]
PK[7]
Pin Function
IQSTAT[3:0]
ADDR[22:20]
ADDR[19:16]
EROMCTL
& Priority
ROMCTL
ACC[2:0]
XCLKS
ECLKX2
MODB
MODA
TAGLO
LSTRB
EWAIT
TAGHI
ECLK
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
XIRQ
GPIO
GPIO
GPIO
LDS
IRQ
mux
mux
GPI
GPI
RW
WE
RE
2
2
2
(1)
3
2
2
3
MC9S12XE-Family Reference Manual Rev. 1.25
I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
O Read enable signal
O Free-running clock output at the Bus Clock rate or programmable
O Low strobe bar output
O Lower data strobe
O Read/write output for external bus
O Write enable signal
O Extended external bus address output
O Extended external bus address output
I
I
I
I
I
I
I
I
I
I
I
I
I
External clock selection input during RESET
Free-running clock output at Core Clock rate (ECLK x 2)
MODB input during RESET
Instruction tagging low pin
Configurable for reduced input threshold
MODA input during RESET
Instruction tagging low pin
Configurable for reduced input threshold
divided in normal modes
EROMON bit control input during RESET
Maskable level- or falling edge-sensitive interrupt input
General-purpose input
Non-maskable level-sensitive interrupt input
General-purpose input
ROMON bit control input during RESET
External Wait signal
Configurable for reduced input threshold
(multiplexed with access master output)
(multiplexed with instruction pipe status bits)
Description
Freescale Semiconductor
Pin Function
dependent
dependent
after Reset
Mode
Mode
4
3
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