ADC-318A Murata Power Solutions, ADC-318A Datasheet - Page 3

• Manufacturer Part Number: ADC-318A
• Description: Analog to Digital Converters - ADC Analog to Digital Converter
• Manufacturer: Murata Power Solutions

Specifications of ADC-318A

• Product Category: Analog to Digital Converters - ADC
• Number Of Channels: 1
• Architecture: Flash
• Conversion Rate: 100 MHz
• Resolution: 8 bit
• Input Type: Single-Ended
• Snr: 46 dB
• Interface Type: Parallel
• Operating Supply Voltage: +/- 5 V, + 5 V
• Maximum Operating Temperature: + 75 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-48
• Maximum Power Dissipation: 960 mW
• Minimum Operating Temperature: - 20 C
• Number Of Converters: 1
• Voltage Reference: External

DATEL
®
Footnotes:
TECHNICAL NOTES
1. The ADC-318 and ADC-318A are ultra high speed full fl ash
➀ VIN = +3V +0.07Vrms
➁ VIH = DGND3–0.8V
➂ VIH = 3.5V
➃ TTL, 0.8 to 2.0V, CL = 5pF
➄ DMUX Mode, CL = 5pF; FC = Clock
PARAMETERS
POWER REQUIREMENTS (cont.)
Power Dissipation
ADC-318
ADC-318A
Operating Temp. Range, Case
Thermal Impedance
Storage Temperature Range
Package Type
Weight
ANALOG IN
+2V to +4V
A/D converters that have 120MHz and 140MHz sampling
rates respectively. The ADC-318 and ADC-318A are fully in-
terchangeable products with the exception of their sampling
rates. Their inputs are TTL, ECL and PECL compatible and
their outputs are TTL compatible. Obtaining fully specifi ed
performance from the ADC-318 and ADC-318A requires that
VIL = DGND3–1.6V
VIL = 0.2V
frequency
ADC-318, 318A
θja
VRT
+4V
A/D CLOCK
Figure 2-1: One Power Supply Operation (TTL, PECL)
V
+2V
RB
1 2
+
+
5V(A)
15
13
14
48
47
46
11
2
4
6
7
9
+
3 10
5
8
–20
–65
—
➅ Straight Mode, CL = 5pF
➆ CL = 5pF
➇ VIN = FS, DMUX mode
➈ VIN = FS, DMUX mode, Error >16LSB
➉ VIN = FS, Straight mode, Error >16LSB
680
570
11
12
12
1
"Times Per Sample"
Mounted on 50x50mm, 1.6mm thick
glass fi ber base epoxy board
19 30 31 42
20 29
®
0.25 ounces (0.7 grams)
5V(D)
62.5
48-pin, plastic QFP
• 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: [phone] • www.datel.com • e-mail: [e-mail]
32 41
—
—
780
790
Note: All capacitors not otherwise designated are 0.1μF
+
43
44
45
+150
28 B BIT 1
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
23 B BIT 6
22 B BIT 7
21 B BIT 8
LSB
TTL
CLOCK OUT
MSB
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
35 A BIT 6
34 A BIT 7
33 A BIT 8
LSB
MSB
+75
980
960
—
°C/Watt
mW
mW
°C
°C
5V(D)
5V(D)
8-Bit, 120MHz and 140MHz Full-Flash A/D Converter
2. Power supply lines and grounding may effect the perfor-
3. The analog input terminal (pin 6) has 21pF of input capaci-
4. The use of a buffer amplifi er and bypass capacitors is also
ANALOG IN
the characteristic impedance of all input/output logic and
analog input lines be properly matched.
recommended on the reference input terminals VRT (pin 11)
and VRB (pin 2). The analog input range is determined by
+2V to +4V
mance of the ADC-318 and ADC-318A. Separate and
substantial AGND and DGND ground planes are required.
These grounds have to be connected to one earth point
underneath the device. There are three digital grounds,
DGND1 (pin 29), DGND2 (pins 20, 32, 41) and DGND3 (pin
12). These DGND 's are separated internally. DGND1 and
DGND2 are always connected externally but DGND3 shall
be connected differently depending on whether the single or
dual power supply mode is used, as explained later.
The ADC-318 and ADC-318A have separate +AVs and
+DVs pins. It is recommended that both +AVs and +DVs
be powered from a single source. Other external digital
circuits must be powered with a separate +DVs. Layouts of
+AVs and +DVs lines must be separated like the GND lines
to avoid mutual interference and are connected to a point
through an LC fi lter. There are two digital supplies +DVs1
(pin 30) and +DVs2 (pins 19, 31, 42). These are also sepa-
rated internally. These must be tied together outside while
in use. Bypassing all power lines with a 0.1uF ceramic chip
capacitor and the use of multilayered PC boards is recom-
mended.
tance. The input signal has to be given via a buffer amplifi er
which has enough driving power. Make lead wires as short
as possible and use chip resistors and capacitors to avoid
parasitic capacitance and inductance.
ECL
VRT
+4V
V
+2V
A/D CLOCK
A/D CLOCK
RB
Figure 2-2: Two Power Supply Operation (ECL)
+
+
ADC-318, ADC-318A
5V(A)
15
13
14
48
47
46
11
2
4
6
7
9
+
3 10
5
5V(D)
8
1
+
12 20 29
19 30 31 42
30 Mar 2011 ADC-318.B02 Page 3 of 8
5V(D)
32 41
+
43
44
45
28 B BIT 1
27 B BIT 2
26 B BIT 3
25 B BIT 4
24 B BIT 5
23 B BIT 6
22 B BIT 7
21 B BIT 8
LSB
TTL
CLOCK OUT
MSB
40 A BIT 1
39 A BIT 2
38 A BIT 3
37 A BIT 4
36 A BIT 5
35 A BIT 6
34 A BIT 7
33 A BIT 8
LSB
MSB
5V(D)
5V(D)