AK5701VNP AKM Semiconductor Inc, AK5701VNP Datasheet
AK5701VNP
Specifications of AK5701VNP
AK5701VNP
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AK5701VNP Summary of contents
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The AK5701 features a 16-bit stereo ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports base-band clock of mobile phone, therefore it is easy ...
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Block Diagram LIN1 RIN1 S E LIN2 L RIN2 MPWR VCOM AVDD AVSS VCOC PLL MCKO MCKI MS0404-E-02 ALC Audio I/F or ADC HPF MIX Controller IVOL Control Register CSP CSN CCLK CDTI Figure 1. Block Diagram - 2 ...
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Ordering Guide AK5701VN AK5701KN AKD5701 ■ Pin Layout 19 MPWR 20 RIN2 21 LIN2 22 RIN1 23 LIN1 24 VCOC ■ Comparison with AK5355VN Function Input Selector Input Gain Mic Bias ALC Mono Mic Mode Audio I/F Format PLL ...
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No. Pin Name I/O 1 VCOM O 2 AVSS - 3 AVDD - 4 DVDD - 5 DVSS - 6 BCLK O 7 LRCK O 8 SDTO O 9 CSP I 10 MCKO O 11 EXSDTI I 12 EXLRCK I ...
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DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital |AVSS – DVSS| Input Current, Any Pin Except Supplies Analog Input Voltage (Note 4) Digital Input Voltage (Note 5) Ambient Temperature (powered applied) Storage Temperature Note 2. All voltages with respect ...
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AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits ...
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AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; fs=44.1kHz) Parameter ADC Digital Filter (Decimation LPF): Passband (Note 15) Stopband (Note 15) Passband Ripple Stopband Attenuation Group Delay (Note 16) Group Delay Distortion ADC Digital Filter (HPF): HPF1-0 bits = “00” Frequency ...
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AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; C Parameter PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency Pulse Width Low Pulse Width High MCKO Output Timing Frequency Duty Cycle Except 256fs at fs=32kHz, 29.4kHz 256fs ...
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Parameter PLL Slave Mode (PLL Reference Clock = EXBCLK pin) EXLRCK Input Timing Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle EXBCLK Input Timing Period PLL3-0 bits = “0010” PLL3-0 bits = “0011” Pulse Width Low Pulse ...
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Parameter Audio Interface Timing (DSP Mode) Master Mode LRCK “↑” to BCLK “↑” (Note LRCK “↑” to BCLK “↓” (Note BCLK “↑” to SDTO (BCKP bit = “0”) BCLK “↓” to SDTO (BCKP bit = “1”) Slave Mode EXLRCK “↑” ...
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Parameter Control Interface Timing (CSP pin = “L”) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN Edge to CCLK “↑” (Note CCLK “↑” to CSN Edge (Note Control Interface ...
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Timing Diagram MCKI LRCK BCLK MCKO LRCK BCLK (BCKP = "0") BCLK (BCKP = "1") SDTO Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”) MS0404-E-02 1/fCLK tCLKH tCLKL 1/fs tLRCKH tLRCKL Duty = ...
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LRCK BCLK (BCKP = "1") BCLK (BCKP = "0") SDTO Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) LRCK BCLK SDTO Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode) MS0404-E-02 ...
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EXLRCK EXBCLK (BCKP = "0") EXBCLK (BCKP = "1") Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0) EXLRCK EXBCLK (BCKP = "1") EXBCLK (BCKP = "0") Figure ...
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MCKI EXLRCK EXBCLK MCKO Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) EXLRCK EXBCLK (BCKP = "0") EXBCLK (BCKP = "1") SDTO Figure 9. Audio Interface Timing (PLL Slave mode & ...
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EXLRCK EXBCLK (BCKP = "1") EXBCLK (BCKP = "0") SDTO Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MCKI EXLRCK EXBCLK MS0404-E-02 tLRCKH tLRB tBSD 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH ...
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EXLRCK tBLR EXBCLK SDTO Figure 12. Audio Interface Timing (PLL/EXT Slave mode) MS0404-E-02 tLRB tLRD tBSD MSB - 17 - [AK5701] VIH VIL VIH VIL 50%DVDD 2007/08 ...
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CSN CCLK CDTI Figure 13. WRITE Command Input Timing (CSP pin = “L”) CSN CCLK CDTI D2 Figure 14. WRITE Data Input Timing (CSP pin = “L”) MS0404-E-02 tCSS tCCKL tCCKH tCDS C1 C0 tCSH ...
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CSN CCLK CDTI Figure 15. WRITE Command Input Timing (CSP pin = “H”) CSN CCLK CDTI D2 Figure 16. WRITE Data Input Timing (CSP pin = “H”) MS0404-E-02 tCSS tCCKL tCCKH tCDS C1 C0 tCSH ...
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PMADL bit or PMADR bit SDTO PDN MS0404-E-02 tPDV Figure 17. Power Down & Reset Timing 1 tPD Figure 18. Power Down & Reset Timing [AK5701] 50%DVDD VIL 2007/08 ...
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System Clock There are the following five clock modes to interface with external devices Mode PLL Master Mode (Note 25) PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK ...
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PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in PLL is powered-up (PMPLL bit ...
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When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits (Table 6). FS3 bit FS2 bit Mode Others Table 6. Setting of Sampling Frequency ...
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PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated by ...
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PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, EXBCLK or EXLRCK pin. The required clock to the AK5701 is generated by an ...
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EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK5701 becomes EXT mode. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. This mode is ...
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EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”) The AK5701 becomes EXT Master Mode by setting as PLL circuit is not operated. The clock required to operate is ...
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Bypass Mode When THR bit = “1”, M/S bit = “0”, PMADL bit = “0” and PMADR bit = “0”, input clocks and data of EXLRCK, EXBCLK and EXSDTI pins are bypassed to LRCK, BCLK and SDTO pins, respectively. ...
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Audio Interface Format Fore types of data format are available and are selected by setting the DIF1-0 bits is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes, but DSP Mode ...
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EXLRCK LRCK EXBCLK(32fs) BCLK(32fs) Lch 8 SDTO( 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”, M/S = “0” or “1”) EXLRCK LRCK EXBCLK(32fs) ...
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LRCK BCLK(32fs) Lch SDTO( BCLK(64fs) Lch SDTO( 15:MSB, 0:LSB Figure 30. Mode 1 Timing (BCKP = “0”, MSBS = “0”, M/S = “1”) ...
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EXLRCK LRCK EXBCLK(32fs) BCLK(32fs SDTO( EXBCLK(64fs) BCLK(64fs SDTO(o) 15:MSB, 0:LSB Figure 34. Mode 2 Timing (MSB justified, M/S = “0” or “1”) EXLRCK ...
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Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is selected by HPF1-0 bits (Table 18) and scales with sampling rate (fs). The default value is ...
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Figure 37. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”) ■ MIC Gain Amplifier The AK5701 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits 20). The typical input impedance ...
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ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. 1. ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level and IVR ...
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ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits If the input signal does not exceed “ALC recovery waiting counter reset level” recovery operation is executed. The IVL and IVR values are automatically incremented by RGAIN1-0 ...
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Example of ALC Operation Table 28 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH Limiter detection Level ZELMN Limiter zero crossing detection ZTM1-0 Zero crossing timeout period Recovery waiting period WTM1-0 *WTM1-0 bits ...
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Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. After exiting reset state, set-up the registers for the ALC operation ...
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When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written in an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write ...
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Serial Control Interface Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The CSP pin selects the polarity of the CSN pin and chip address. 1) CSP pin = “L” The data ...
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Register Map Addr Register Name 10H Power Management 11H PLL Control 12H Signal Select 13H Mic Gain Control 14H Audio Format Select 15H fs Select 16H Clock Output Select 17H Volume Control 18H Lch Input Volume Control 19H Rch ...
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Register Definitions Addr Register Name 10H Power Management Default PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power down (default) 1: Power up PMADR: MIC-Amp Rch and ADC Rch Power Management 0: Power down (default) 1: Power up ...
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Addr Register Name 12H Signal Select Default INL: ADC Lch Input Source Select 0: LIN1 pin (default) 1: LIN2 pin INR: ADC Rch Input Source Select 0: RIN1 pin (default) 1: RIN2 pin MDIF1: ADC Lch Input Type Select 0: ...
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Addr Register Name 15H fs Select Default FS3-0: Sampling Frequency Select ( Default: “1111” (44.1kHz) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. BCKO1-0: BCLK Output Frequency Select at Master Mode Default: “01” (32fs) ...
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Addr Register Name 1AH Timer Select Default WTM1-0: ALC Recovery Waiting Period Default: “00” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period Default: “00” (128/fs) Addr Register Name 1BH ALC Mode Control 1 Default REF7-0: Reference Value at ALC ...
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Addr Register Name 1DH Mode Control 1 Default TE3-0: EXT Master Mode Enable When TE3-0 bits is set to “0101”, the write operation to addr=1EH is enabled. TE3-0 bits should be set to “1010” except for EXT Master Mode. TE3-0 ...
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Figure 43 and Figure 44 shows the system connection diagram for the AK5701. The evaluation board [AKD5701] demonstrates the optimum layout, power supply arrangements and measurement results. External MIC Internal MIC 0 (Note) Notes: - AVSS and DVSS ...
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Line In 0 (Note) Notes: - AVSS and DVSS of the AK5701 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK5701 is EXT ...
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Grounding and Power Supply Decoupling The AK5701 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not ...
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Clock Set up When ADC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (4) MCKO bit (Addr:16H, D2) PMPLL bit (Addr:11H, D0) MCKI pin M/S ...
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PLL Slave Mode (EXLRCK or EXBCLK pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of ...
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PLL Slave Mode (MCKI pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (4) MCKO bit (Addr:16H, D2) PMPLL bit (Addr:11H, D0) MCKI pin MCKO pin EXBCLK pin EXLRCK pin <Example> (1) After Power Up: PDN ...
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EXT Slave Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) MCKI pin EXLRCK pin EXBCLK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the ...
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EXT Master Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) MCKI pin M/S bit (Addr:11H, D1) TE3-0 bits "1010" (Addr:1DH, D7-4) TMASTER bit (Addr:1EH, D1) BCLK pin LRCK pin <Example> (1) After Power Up: PDN ...
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Slave & Bypass Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more ...
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Bypass Mode Power Supply (1) PDN pin (2) THR bit (Addr:16H, D3) EXLRCK pin EXBCLK pin EXSDTI pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5701. (2) ...
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MIC Input Recording (Stereo) FS3-0 bits X,XXX (Addr:15H, D3-0) (1) MIC Control 0, 01 (Addr:12H, D4 (2) & Addr:13H, D1-0) Timer Control XXH (Addr:1AH) (3) ALC Control 1 XXH (Addr:1BH) (4) ALC Control 2 XXH (Addr:1CH) ALC State ALC Disable ...
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Stop of Clock Master clock can be stopped when ADC is not used. 1. PLL Master Mode (1) PMPLL bit (Addr:11H, D0) M/S bit (Addr:11H, D1) (2) MCKO bit "H" or "L" (Addr:16H, D2) (3) External MCKI Input <Example> ...
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PLL Slave Mode (MCKI pin) (1) PMPLL bit (Addr:11H, D0) (2) MCKO bit (Addr:16H, D2) External MCKI Input <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO output: MCKO bit = “1” → “0” ...
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Power down Power supply current is typ. 20μA by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be shut down (typ. 1μA) by stopping clocks and setting ...
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QFN (Unit: mm) 4.0 ± 0 0.08 0.5 Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Material & Lead finish Package molding compound: Lead frame ...
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AK5701VN AK5701KN MS0404-E-02 MARKING 5701 XXXX 1 XXXX : Date code identifier (4 digits) 5701K XXXX 1 XXXX : Date code identifier (4 digits [AK5701] 2007/08 ...
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Date (YY/MM/DD) Revision 05/08/04 00 05/11/22 01 07/08/30 02 MS0404-E-02 REVISION HISTORY Reason Page Contents First Edition Error correction 8 Switching Characteristics (PLL Slave Mode) tBCKL(min): 240ns tBCKH(min): 240ns 25 PLL Slave Mode a) Mode 1: EXBCLK or EXLRCK b) ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status ...