AK5701VNP AKM Semiconductor Inc, AK5701VNP Datasheet - Page 57

• Manufacturer Part Number: AK5701VNP
• Description: IC ADC AUDIO STER 16BIT 24QFN
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5701VNP

• Resolution (bits): 16 b
• Sampling Rate (per Second): 7.35k ~ 48k
• Data Interface: I²S, Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1039-2; AK5701VNP

MS0404-E-02
& Addr:13H, D1-0)
ALC Control 2
ALC Control 1
Timer Control
ADC Internal
MIC Input Recording (Stereo)
MIC Control
(Addr:15H, D3-0)
PMADL/R bit
(Addr:10H, D1-0)
<Example>
(Addr:12H, D4
ALC State
FS3-0 bits
(Addr:1CH)
(Addr:1AH)
(Addr:1BH)
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“Figure
State
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK5701 is PLL mode, MIC and ADC should be powered-up
(2) Set up MIC input (Addr: 12H&13H)
(3) Set up Timer Select for ALC (Addr: 1AH)
(4) Set up REF value for ALC (Addr: 1BH)
(5) Set up LMTH1-0, RGAIN1-0, LMAT1-0 and ALC bits (Addr: 1CH)
(6) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1”
(7) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0”
(8) ALC Disable: ALC bit = “1” → “0”
When the registers for the ALC operation are not changed, ALC bit may be kept as “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be executed after the AK5701 goes to the manual mode (ALC
bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADC or PMADR
bit is changed to “1”.
in consideration of PLL lock time after a sampling frequency is changed.
The initialization cycle time of ADC is 3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = “00”.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (0dB).
To start the recording within 100ms, the following sequence is required.
(6a) PMVCM=PMMP bits = “1”.
(6b) Wait for 2ms, then PMPLL bit = “1”.
(6c) Wait for 6ms, then PMADL=PMADR bits = “1”.
39”.
X,XXX
0, 01
XXH
XXH
XXH
(1)
ALC Disable
Power Down
(2)
(3)
(4)
(5)
Figure 52. MIC Input Recording Sequence
(6)
Initialize Normal State Power Down
3088 / fs
ALC Enable
1111
1, 01
0AH
E1H
81H
- 57 -
(7)
ALC Disable
(8)
01H
Example:
Pre MIC AMP:+15dB
PLL Master Mode
Audio I/F Format:I2S
Sampling Frequency:44.1kHz
MIC Power On
ALC setting:Refer to Figrure 37
(1) Addr:15H, Data:2FH
(3) Addr:1AH, Data:0AH
(4) Addr:1BH, Data:E1H
ALC bit = “1”
(5) Addr:1CH, Data:81H
(8) Addr:1CH, Data:01H
(2) Addr:12H, Data:10H
(6) Addr:10H, Data:07H
(7) Addr:10H, Data:04H
Addr:13H, Data:01H
Recording
[AK5701]
2007/08