AK5701VNP AKM Semiconductor Inc, AK5701VNP Datasheet - Page 29

• Manufacturer Part Number: AK5701VNP
• Description: IC ADC AUDIO STER 16BIT 24QFN
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5701VNP

• Resolution (bits): 16 b
• Sampling Rate (per Second): 7.35k ~ 48k
• Data Interface: I²S, Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1039-2; AK5701VNP

DIF1
■
Fore types of data format are available and are selected by setting the DIF1-0 bits
is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes, but DSP Mode
1 supports PLL Master Mode only. LRCK, BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and
SDTO pins are used in slave mode. In modes 2 and 3, the SDTO is clocked out on the falling edge (“↓”) of
BCLK/EXBCLK.
In Modes 0 and 1 (DSP mode 0 and 1), the audio I/F timing is changed by BCKP and MSBS bits.
When BCKP bit is “0”, SDTO data is output by rising edge (“↑”) of BCLK/EXBCLK.
When BCKP bit is “1”, SDTO data is output by falling edge (“↓”) of BCLK/EXBCLK.
MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK.
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1”
at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data
and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit
data.
MS0404-E-02
0
0
Audio Interface Format
Mode
0
1
2
3
DIF0
0
1
DIF1 bit
MSBS
0
0
1
1
0
0
1
1
0
0
1
1
BCKP
DIF0 bit
0
1
0
1
0
1
0
1
0
1
0
1
MSB of SDTO is output by the rising edge (“↑”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
26).
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
27).
MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure
MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure
MSB of SDTO is output by the rising edge (“↑”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
30).
MSB of SDTO is output by the falling edge (“↓”) of the first
BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
31).
MSB of SDTO is output by next rising edge (“↑”) of the falling edge (“↓”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure
MSB of SDTO is output by next falling edge (“↓”) of the rising edge (“↑”)
of the first BCLK/EXBCLK after the rising edge (“↑”) of LRCK/EXLRCK
(Figure
Table 16. Audio Interface Format in Mode 0, 1
28).
29).
32).
33).
Table 15. Audio Interface Format
I
MSB justified
DSP Mode 0
DSP Mode 1
2
S compatible
SDTO
- 29 -
Audio Interface Format
BCLK, EXBCLK
≥ 32fs
≥ 32fs
≥ 32fs
32fs
(Table
15). In all modes, the serial data
See
Figure 34
Figure 35
Figure
Table 16
(Figure
(Figure
(Figure
(Figure
(default)
[AK5701]
2007/08
(default)