AK5701VNP AKM Semiconductor Inc, AK5701VNP Datasheet - Page 50

IC ADC AUDIO STER 16BIT 24QFN

AK5701VNP

Manufacturer Part Number
AK5701VNP
Description
IC ADC AUDIO STER 16BIT 24QFN
Manufacturer
AKM Semiconductor Inc
Type
ADCr
Datasheet

Specifications of AK5701VNP

Resolution (bits)
16 b
Sampling Rate (per Second)
7.35k ~ 48k
Data Interface
I²S, Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3V
Operating Temperature
-30°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
974-1039-2
AK5701VNP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AK5701VNP-L
Manufacturer:
AKM Semiconductor Inc
Quantity:
1 874
Part Number:
AK5701VNP-L
Manufacturer:
ST
Quantity:
7 190
When ADC is powered-up, the clocks must be supplied.
MS0404-E-02
Power Supply
PMVCM bit
(Addr:10H, D2)
(Addr:16H, D2)
(Addr:11H, D0)
(Addr:11H, D1)
PMPLL bit
BCLK pin
LRCK pin
MCKO pin
Clock Set up
1. PLL Master Mode.
<Example>
MCKO bit
MCKI pin
PDN pin
M/S bit
(1) After Power Up, PDN pin “L”
(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows.
(3) Power UpVCOM: PMVCM bit = “0”
(4) In case of using MCKO output: MCKO bit = “1”
(5) PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source.
(6) The AK5701 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation
(7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
“L” time of 150ns or more is needed to reset the AK5701.
(2a) M/S bit = “1” and setting of PLL3-0, FS3-0, BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
VCOM should first be powered-up before the other block operates.
In case of not using MCKO output: MCKO bit = “0”
PLL lock time is 40ms(max) at MCKI=12MHz
starts.
(1)
(2)
(3)
(4)
(5)
Figure 45. Clock Set Up Sequence (1)
40msec(max)
(7)
40msec(max)
“H”
CONTROL SEQUENCE
Input
“1”
(Table
(6)
(8)
- 50 -
Output
Output
4).
Example:
(1) Power Supply & PDN pin = “L”
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Audio I/F Format: I2S
MCKO: Enable
Sampling Frequency: 44.1kHz
MCKO, BCLK and LRCK output
(2)Addr:11H, Data:12H
(4)Addr:16H, Data:04H
(3)Addr:10H, Data:04H
Addr:15H, Data:2FH
Addr:14H, Data:23H
Addr:11H, Data:13H
[AK5701]
“H”
2007/08

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