AK4382AVT AKM Semiconductor Inc, AK4382AVT Datasheet
AK4382AVT
Specifications of AK4382AVT
AK4382AVT
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AK4382AVT Summary of contents
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ASAHI KASEI The AK4382A offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit architecture for its modulator the AK4382A delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4382A has ...
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... ASAHI KASEI n Ordering Guide AK4382AVT -40 +85 C AKD4382 Evaluation Board for AK4382A n Pin Layout MCLK BICK SDTI LRCK PDN CSN CCLK CDTI No. Pin Name I/O 1 MCLK I 2 BICK I 3 SDTI I 4 LRCK I 5 PDN I 6 CSN I 7 CCLK I 8 CDTI I 9 AOUTR- ...
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ASAHI KASEI (VSS=0V; Note 1) Parameter Power Supply Input Current (any pins except for supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note: 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in ...
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ASAHI KASEI (Ta=25 C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; R Parameter Resolution Dynamic Characteristics THD+N fs=44.1kHz BW=20kHz fs=96kHz BW=40kHz fs=192kHz BW=40kHz Dynamic Range (-60dBFS with A-weighted) S/N (A-weighted) Interchannel Isolation (1kHz) Interchannel Gain Mismatch ...
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ASAHI KASEI SHARP ROLL-OFF FILTER CHARACTERISTICS ( VDD = 4.75 5.25V 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Digital filter Passband 0.05dB (Note 9) -6.0dB Stopband (Note 9) Passband Ripple Stopband Attenuation Group Delay ...
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ASAHI KASEI (Ta=25 C; VDD=4.75 5.25V; C =20pF) L Parameter Master Clock Frequency Duty Cycle LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle Audio Interface Timing BICK Period Normal Speed Mode Double/Quad Speed Mode BICK ...
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ASAHI KASEI n Timing Diagram MCLK tCLKH LRCK BICK tBCKH LRCK tBLR BICK SDTI MS0071-E-02 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Serial Interface Timing - 7 - [AK4382A] VIH VIL ...
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ASAHI KASEI CSN tCSS CCLK CDTI C1 CSN CCLK CDTI D3 PDN MS0071-E-02 tCCKL tCCKH tCDS tCDH C0 R/W WRITE Command Input Timing WRITE Data Input Timing tPD Power-down Timing - 8 - [AK4382A] VIH VIL VIH ...
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ASAHI KASEI n System Clock The external clocks, which are required to operate the AK4382A, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to ...
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ASAHI KASEI Table 5. Sampling Speed (Auto Setting Mode: Default) LRCK fs 128fs 192fs 32.0kHz - - 44.1kHz - - 48.0kHz - - 88.2kHz - - 96.0kHz - - 176.4kHz 22.5792 33.8688 192.0kHz 24.5760 36.8640 Table 6. System Clock Example ...
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ASAHI KASEI LRCK BICK (32fs) SDTI Mode BICK (64fs) SDTI Don’t care Mode 0 15:MSB, 0:LSB Lch Data LRCK BICK (64fs) SDTI Don’t care Mode ...
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ASAHI KASEI LRCK BICK (64fs) SDTI 23 22 23:MSB, 0:LSB n De -emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with ...
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ASAHI KASEI n Zero Detection The AK4382A has channel-independent zeros detect function. When the input data at each channel is continuously zero s for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel ...
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ASAHI KASEI n System Reset The AK4382A should be reset once by bringing PDN= ”L” upon power-up. The AK4382A is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by ...
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ASAHI KASEI n Reset Function When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by ...
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ASAHI KASEI n Mode Control Interface Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write ...
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ASAHI KASEI n Register Definitions Addr Register Name D7 00H Control 1 ACKS default 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation When MCLK frequency or DFS change s , the AK4382A ...
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ASAHI KASEI DZFM: Data Zero Detect Mode 0: Channel Separated Mode 1: Channel ANDed Mode If the DZFM bit is set to “ 1”, the DZF pins of both channels go to “ H” only when the input data at ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1 F ceramic capacitor for high frequency should be placed as near to ...
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ASAHI KASEI 16pin TSSOP (Unit: mm) *5.0 0 0.22 0.1 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: ...
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ASAHI KASEI These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...