AK4382AVT AKM Semiconductor Inc, AK4382AVT Datasheet - Page 9

• Manufacturer Part Number: AK4382AVT
• Description: IC DAC 24BIT DIFF 16TSSOP
• Manufacturer: AKM Semiconductor Inc

Specifications of AK4382AVT

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Other names: 974-1009-2; AK4382AVT

ASAHI KASEI
n System Clock
The external clocks, which are required to operate the AK4382A, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter
and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”:
Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “ ”), the AK4382A is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the
appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4382A is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4382A may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4382A should be reset by PDN= “L” after threse clocks are provided. If the
external clocks are not present, the AK4382A should be in the power-down mode (PDN= “L”). After exiting reset at
power-up etc., the AK4382A is in the power-down mode until MCLK and LRCK are input.
MS0071-E-02
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
LRCK
LRCK
fs
fs
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
11.2896MHz
12.2880MHz
11.2896MHz
12.2880MHz
8.1920MHz
DFS1
0
0
1
256fs
128fs
176.4kHz
192.0kHz
LRCK
fs
Table 1. Sampling Speed (Manual Setting Mode)
DFS0
0
1
0
12.2880MHz
16.9344MHz
18.4320MHz
16.9344MHz
18.4320MHz
22.5792MHz
24.5760MHz
OPERATION OVERVIEW
384fs
192fs
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
128fs
MCLK
MCLK
MCLK
16.3840MHz
22.5792MHz
24.5760MHz
22.5792MHz
24.5760MHz
- 9 -
33.8688MHz
36.8640MHz
512fs
256fs
Sampling Rate (fs)
192fs
24.5760MHz
33.8688MHz
36.8640MHz
33.8688MHz
36.8640MHz
11.2896MHz
12.2880MHz
120kHz~216kHz
768fs
384fs
8kHz~54kHz
60kHz~108z
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
BICK
BICK
64fs
64fs
Default
[AK4382A]
2002/12