AK4382AVT AKM Semiconductor Inc, AK4382AVT Datasheet - Page 16

• Manufacturer Part Number: AK4382AVT
• Description: IC DAC 24BIT DIFF 16TSSOP
• Manufacturer: AKM Semiconductor Inc

Specifications of AK4382AVT

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Settling Time: -
• Other names: 974-1009-2; AK4382AVT

ASAHI KASEI
n Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of
Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and
Control Data (MSB first, 8bits). AK4382A latches the data on the rising edge of CCLK, so data should clocked in on the
falling edge. The writing of data becomes valid by CSN “ ”. The clock speed of CCLK is 5MHz (max). The CSN must be fixed
to “H” when the register does not be accessed.
PDN = “L” resets the registers to their default values. The int ernal timing circuit is reset by RSTN bit, but the registers are
not initialized.
*The AK4382A does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4382A is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
n Register Map
Notes:
MS0071-E-02
Addr
00H
01H
02H
03H
04H
is inhibited.
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values.
All data can be written to the register even if PW or RSTN bit is “0”.
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
Register Name
CCLK
CSN
CDTI
ACKS
ATT7
ATT7
DZFE
C1
0
D7
0
C0
1
R/W
2
C1-C0:
R/W:
A4-A0: Register Address
D7-D0:
DZFM
ATT6
ATT6
A4
D6
3
0
0
Figure 8. Control I/F Timing
A3
4
READ/WRITE (Fixed to “1”, Write only)
Control Data
A2
5
SLOW
ATT5
ATT5
Chip Address (Fixed to “01”)
D5
A1
0
0
6
- 16 -
A0
7
D7
8
ATT4
ATT4
DFS1
DIF2
D4
D6
0
9
D5
10 11 12 13 14 15
D4
ATT3
ATT3
DFS0
DIF1
D3
0
D3
D2
D1
DEM1
DZFB
ATT2
ATT2
DIF0
D2
D0
DEM0
ATT1
ATT1
PW
D1
0
[AK4382A]
SMUTE
RSTN
ATT0
ATT0
2002/12
D0
0