STM32F207ICH6 STMicroelectronics, STM32F207ICH6 Datasheet - Page 128

• Manufacturer Part Number: STM32F207ICH6
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex M3 CAM 256 kB
• Manufacturer: STMicroelectronics

Specifications of STM32F207ICH6

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M3
• Data Bus Width: 32 bit

Electrical characteristics
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Synchronous waveforms and timings
Figure 58
Table 77
with the following FSMC configuration:
●
●
●
●
●
In all timing tables, the
Figure 58. Synchronous multiplexed NOR/PSRAM read timings
FSMC_AD[15:0]
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b)
FSMC_A[25:16]
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
FSMC_NADV
FSMC_NOE
FSMC_CLK
FSMC_NEx
BurstAccessMode = FSMC_BurstAccessMode_Enable;
MemoryType = FSMC_MemoryType_CRAM;
WriteBurst = FSMC_WriteBurst_Enable;
CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
t d(CLKL-NADVL)
t d(CLKL-ADV)
provide the corresponding timings. The results shown in these tables are obtained
through
t w(CLK)
Figure 61
T
HCLK
t d(CLKL-ADIV)
t d(CLKL-NExL)
t d(CLKL-AV)
AD[15:0]
represent synchronous waveforms and
is the HCLK clock period.
Doc ID 15818 Rev 9
t su(NWAITV-CLKH)
t su(NWAITV-CLKH)
t d(CLKL-NADVH)
t su(ADV-CLKH)
Data latency = 0
t w(CLK)
t su(NWAITV-CLKH)
D1
t d(CLKH-NOEL)
t su(ADV-CLKH)
t h(CLKH-ADV)
t h(CLKH-NWAITV)
t h(CLKH-NWAITV)
t h(CLKH-NWAITV)
t d(CLKL-NOEH)
t d(CLKL-NExH)
D2
Table 75
BUSTURN = 0
t d(CLKL-AIV)
t h(CLKH-ADV)
STM32F20xxx
through
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