STM32F207ICH6 STMicroelectronics, STM32F207ICH6 Datasheet - Page 23

• Manufacturer Part Number: STM32F207ICH6
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex M3 CAM 256 kB
• Manufacturer: STMicroelectronics

Specifications of STM32F207ICH6

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M3
• Data Bus Width: 32 bit

STM32F20xxx
a.
Regulator ON
The regulator ON modes are activated by default on LQFP packages.On WLCSP66
package, they are activated by connecting both REGOFF and IRROFF pins to V
only REGOFF must be connected to V
V
There are three regulator ON modes:
●
●
●
Regulator OFF
●
●
V
and IRROFF is set to V
DD
DD
minimum value is 1.8 V
minimum value is 1.7 V when the device operates in the 0 to 70 °C temperature range
MR is used in nominal regulation mode (Run)
LPR is used in Stop mode
Power-down is used in Standby mode:
The regulator output is in high impedance: the kernel circuitry is powered down,
inducing zero consumption (but the contents of the registers and SRAM are lost).
Regulator OFF/internal reset ON
On WLCSP66 package, this mode is activated by connecting REGOFF pin to V
IRROFF pin to V
(IRROFF not available).
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
In this mode, PA0 cannot be used as a GPIO pin since it allows to reset the part of the
1.2 V logic which is not reset by the NRST pin, when the internal voltage regulator in
OFF.
Regulator OFF/internal reset OFF
On WLCSP66 package, this mode activated by connecting REGOFF to V
IRROFF to V
is available only on the WLCSP package. It allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
–
V
between power domains.
If the time for V
reach 1.8 V
Otherwise, PA0 should be asserted low externally during POR until V
1.8 V (see
V
between power domains (see
PA0 should be kept low to cover both conditions: until V
1.08 V, and until V
NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
DD
should always be higher than V
should always be higher than V
DD
. IRROFF cannot be activated in conjunction with REGOFF. This mode
Figure
(a)
SS
CAP_1
CAP_1
DD
, then PA0 should be connected to the NRST pin (see
. On UFBGA176 package, only REGOFF must be connected to V
CAP_1
.
7).
DD
(a)
and V
and V
DD
.
Doc ID 15818 Rev 9
reaches 1.65 V.
and V
is below 1.65 V (see
CAP_2
CAP_2
CAP_2
SS
Figure
pins, in addition to V
pins, in addition to V
on UFBGA176 package (IRROFF is not available).
to reach 1.08 V is faster than the time for V
CAP_1
CAP_1
6).
and V
and V
Figure
CAP_2
CAP_2
7).
DD
DD
.
.
to avoid current injection
to avoid current injection
CAP_1
and V
CAP_2
Figure
SS
DD
Description
SS
and
reaches
, while
reach
DD
6).
23/177
DD
and
DD
to