MPC8536CVTATLA Freescale Semiconductor, MPC8536CVTATLA Datasheet - Page 48

• Manufacturer Part Number: MPC8536CVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536CVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

At recommended operating conditions with L/TV
Clock period for TBI Receive Clock 0, 1
Skew for TBI Receive Clock 0, 1
Duty cycle for TBI Receive Clock 0, 1
RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1
RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1
Clock rise time (20%-80%) for TBI Receive Clock 0, 1
Clock fall time (80%-20%) for TBI Receive Clock 0, 1
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.
Electrical Characteristics
2.9.2.4.2
This table provides the TBI receive AC timing specifications.
48
for inputs and t
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of
t
R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
These two clock signals are also referred as PMA_RX_CLK[0:1].
TRX
represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
(first two letters of functional block)(reference)(state)(signal)(state)
TBI Receive AC Timing Specifications
GTX_CLK
Parameter/Condition
TCG[9:0]
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 33. TBI Receive AC Timing Specifications
TRX
Figure 22. TBI Transmit AC Timing Diagram
t
TTXH
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
2
t
TTKHDV
DD
TRDXKH
t
TTXF
of 3.3 V ± 5%.
t
TTX
symbolizes TBI receive timing (TR) with respect to the time data input signals
t
Symbol
TRXH
t
t
TRDXKH
t
TRDVKH
t
SKTRX
t
t
t
TRXR
TRXF
TTXF
TRX
/t
TRX
for outputs. For example, t
1
(first two letters of functional block)(signal)(state) (reference)(state)
t
TTKHDX
t
TTXR
Min
7.5
2.5
1.5
0.7
0.7
40
—
t
16.0
TTXR
Typ
—
—
—
—
—
—
TRDVKH
TRX
Freescale Semiconductor
clock reference (K) going
symbolizes TBI receive
Max
8.5
2.4
2.4
60
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%