MPC8536CVTATLA Freescale Semiconductor, MPC8536CVTATLA Datasheet - Page 49

• Manufacturer Part Number: MPC8536CVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536CVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

This figure shows the TBI receive AC timing diagram.
2.9.2.5
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant eTSEC interface.
In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn pin (no receive clock is used on in this
mode, whereas for the dual-clock mode this is the PMA0 receive clock). The 125-MHz transmit clock is applied on the in all
TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in the following table.
Freescale Semiconductor
At recommended operating conditions with LV
RX_CLK clock period
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
TBI Receive Clock 1
TBI Receive Clock 0
(TSECn_RX_CLK)
(TSECn_TX_CLK)
TBI Single-Clock Mode AC Specifications
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
RCG[9:0]
Table 34. TBI single-clock Mode Receive AC Timing Specification
Figure 23. TBI Receive AC Timing Diagram
DD
t
t
SKTRX
/TV
TRXH
t
TRDVKH
DD
of 3.3 V ± 5%
t
TRX
t
TRXH
Valid Data
Symbol
t
t
t
t
TRRDV
TRRDX
t
t
t
TRRH
TRRR
TRRF
TRRJ
TRR
t
TRXF
Valid Data
Min
7.5
2.0
1.0
40
—
—
—
t
TRDXKH
t
TRXR
t
TRDVKH
Typ
8.0
50
—
—
—
—
—
t
TRDXKH
Electrical Characteristics
Max
250
8.5
1.0
1.0
60
—
—
Unit
ns
ps
ns
ns
ns
ns
%
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