MPC8536CVTATLA Freescale Semiconductor, MPC8536CVTATLA Datasheet - Page 99

• Manufacturer Part Number: MPC8536CVTATLA
• Description: Microprocessors - MPU 8536 NON E
• Manufacturer: Freescale Semiconductor

Specifications of MPC8536CVTATLA

• Product Category: Microprocessors - MPU
• Rohs: yes
• Processor Series: PowerQUICC III
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 250 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 512 KB
• Interface Type: I2C, USB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: 0 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-783

UI
V
2.21
This section describes the DC and AC electrical specifications for the PCI Express bus of the chip.
2.21.1
For more information, see
2.21.2
This table lists AC requirements.
2.21.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million 15 (ppm) of each other at all
times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
2.21.4
The following is a summary of the specifications for the physical layer of PCI Express on this chip. For further details as well
as the specifications of the transport and data link layer, please use the PCI Express Base Specification. REV. 1.0a document.
2.21.4.1
This table defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the
component pins.
Freescale Semiconductor
Notes:
1. Tj at BER of 10E-6 86 ps Max.
2. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 42 ps.
3. Limits from “PCI Express CEM Rev 2.0” and measured per “PCI Express Rj, D, and Bit Error Rates”.
Symbol
TX-DIFFp-p
t
t
REFCJ
REFPJ
t
REF
Symbol
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
Phase jitter. Deviation in edge location with respect to mean edge
location
PCI Express
DC Requirements for PCI Express SD1_REF_CLK and
SD1_REF_CLK
AC Requirements for PCI Express SerDes Clocks
Clocking Dependencies
Physical Layer Specifications
Differential Transmitter (TX) Output
MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Unit Interval
Differential
Peak-to-Peak
Output Voltage
Table 70. SD1_REF_CLK and SD1_REF_CLK AC Requirements
Parameter
Section 2.20.2, “SerDes Reference Clocks.”
Table 71. Differential Transmitter (TX) Output Specifications
Parameter Description
399.88
Min
0.8
Nom
400
—
400.12
Max
1.2
Units
ps
V
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note
1.
V
TX-DIFFp-p
Min
–50
—
—
= 2*|V
Typical
10
—
—
TX-D+
Comments
– V
Electrical Characteristics
Max
100
50
—
TX-D-
| See Note 2.
Units
ps
ps
ns
Notes
1,2,3
—
1
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