74LVC646APW NXP Semiconductors, 74LVC646APW Datasheet

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74LVC646APW

Manufacturer Part Number
74LVC646APW
Description
Bus Transceivers OCTAL BUS INTERFACE TRANS/REG
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC646APW

Product Category
Bus Transceivers
Rohs
yes
Package / Case
SOT-355
Mounting Style
SMD/SMT
Factory Pack Quantity
63
Part # Aliases
74LVC646APW,112
1. General description
2. Features and benefits
The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs,
D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly
from the internal registers. Data on the A or B bus is clocked in the internal registers, as
the appropriate clock (CPAB or CPBA) goes to a HIGH logic level. Output enable (OE)
and direction (DIR) inputs are provided to control the transceiver function. In the
transceiver mode, data present at the high-impedance port may be stored in either the A
or B register, or in both. With the select source inputs (SAB and SBA), stored and
real-time (transparent mode) data can be multiplexed. The direction (DIR) input
determines which bus receives data when OE is active (LOW). In the isolation mode (OE
= HIGH), A data may be stored in the B register and/or B data may be stored in the A
register. When an output function is disabled, the input function is still enabled and may be
used to store and transmit data. Only one of the two buses A or B may be driven at a time.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
74LVC646A
Octal bus transceiver/register; 3-state
Rev. 5 — 28 March 2013
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
Complies with JEDEC standard:
ESD protection:
Specified from 40 C to +85 C and 40 C to +125 C.
CC
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
= 0 V
Product data sheet

Related parts for 74LVC646APW

74LVC646APW Summary of contents

Page 1

... Octal bus transceiver/register; 3-state Rev. 5 — 28 March 2013 1. General description The 74LVC646A consists of non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the internal registers. Data on the bus is clocked in the internal registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH logic level ...

Page 2

... Ordering information Type number Package Temperature range Name 40 C to +125 C 74LVC646AD 40 C to +125 C 74LVC646ADB 40 C to +125 C 74LVC646APW 4. Functional diagram Fig 1. Functional diagram 74LVC646A Product data sheet Description SO24 plastic small outline package; 24 leads; body width 7.5 mm SSOP24 plastic shrink small outline package ...

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... NXP Semiconductors CPAB 2 SAB DIR 3 Fig 2. Logic symbol 74LVC646A Product data sheet 23 CPBA 22 SBA 001aab040 Fig 3. All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors OE DIR SBA CPBA SAB CPAB An Fig 4. Logic diagram 74LVC646A Product data sheet MUX identical channels All information provided in this document is subject to legal disclaimers. Rev. 5 — 28 March 2013 74LVC646A Octal bus transceiver/register; 3-state ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO24 and (T)SSOP24 5.2 Pin description Table 2. Pin description Symbol Pin CPAB 1 SAB 2 SBA 22 DIR 3 A[0: 10, 11 B[0:7] 20, 19, 18, 17, 16, 15, 14 CPBA 23 GND 74LVC646A Product data sheet CPAB 1 24 ...

Page 6

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input OE DIR CPAB CPBA     [ HIGH voltage level L = LOW voltage level X = don’t care  ...

Page 7

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 8

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I OFF-state output GND; O current I power-off OFF CC leakage current I supply current I additional per input pin; ...

Page 9

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t enable time and Bn; see DIR to An and Bn; see disable time and Bn; see ...

Page 10

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t hold time An CPAB, CPBA; see maximum see Figure 7 max frequency output skew 3.6 V ...

Page 11

... NXP Semiconductors 11. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 6. Input (An and Bn) to output (Bn and An) propagation delays An, Bn input CPAB, CPBA input Bn, An output Measurement points are given in V and V are typical output voltage levels that occur with the output load ...

Page 12

... NXP Semiconductors Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. The input SAB and SBA to output Bn and An propagation delay times An, Bn LOW-to-OFF OFF-to-LOW HIGH-to-OFF An, Bn OFF-to-HIGH ...

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... NXP Semiconductors DIR input An output An output Bn output Bn output Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 10. The input showing the input DIR to output An, Bn 3-state enable and disable times Table 8. ...

Page 14

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 11. Load circuitry for switching times Table 9 ...

Page 15

... NXP Semiconductors 12. Application information inputs Values for inputs are given in Fig 12. Real-time transfer; bus B to bus A [1] Table 10. Real-time transfer Direction Bus B to bus A Bus A to bus B [ HIGH voltage level LOW voltage level don’t care 74LVC646A Product data sheet ...

Page 16

... NXP Semiconductors inputs Values for inputs are given in Fig 14. Bus A and bus B to storage [1] Table 11. Storage transfer Function Bus A to storage Bus B to storage Bus A and B to storage Storage to bus A Storage to bus B [ HIGH voltage level L = LOW voltage level X = don’t care  ...

Page 17

... NXP Semiconductors 13. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 18

... NXP Semiconductors SSOP24: plastic shrink small outline package; 24 leads; body width 5 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT340-1 Fig 17 ...

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... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... Revision history Document ID Release date 74LVC646A v.5 20130328 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74LVC646A v.4 20040629 74LVC646A v.3 20000621 74LVC646A v ...

Page 21

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 22

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application information Package outline ...

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