74LVT2952PW NXP Semiconductors, 74LVT2952PW Datasheet - Page 2
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74LVT2952PW
Manufacturer Part Number
74LVT2952PW
Description
Bus Transceivers 3.3V OCTAL REG XCVR 3-S
Manufacturer
NXP Semiconductors
Datasheet
1.74LVT2952D-T.pdf
(12 pages)
Specifications of 74LVT2952PW
Product Category
Bus Transceivers
Rohs
yes
Logic Type
BiCMOS
Logic Family
LVT
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
3.8 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Temperature
+ 85 C
Package / Case
TSSOP-24
Function
Registered Transceiver
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Non-Inverting
Factory Pack Quantity
63
Part # Aliases
74LVT2952PW,112
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
2004 Sep 07
24-Pin Plastic SOL
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
SYMBOL
8-bit registered transceiver
Independent registers for A and B buses
Output capability: +64 mA/–32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-State
Latch-up protection exceeds 500 mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
3.3 V Octal registered transceiver (3-State)
I
t
t
C
C
PLH
PHL
CCZ
I/O
IN
PACKAGES
Propagation delay
CPBA to An or
CPAB to Bn
Input capacitance
I/O pin capacitance
Total supply current
OEAB
CPAB
CEAB
GND
B6
B5
B4
B3
B7
B2
B1
B0
10
12
11
1
2
3
4
5
6
7
8
9
PARAMETER
SV00036
15
14
13
24
23
22
21
20
19
18
17
16
V
A7
A6
A5
A4
A3
A2
A1
A0
OEBA
CPBA
CEBA
CC
TEMPERATURE RANGE
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
C
V
Outputs disabled; V
Outputs disabled; V
I
L
= 0 V or 3.0 V
2
= 50 pF; V
DESCRIPTION
The LVT2952 is a high-performance BiCMOS product designed for
V
This device combines low static and dynamic power dissipation with
high speed and high output drive.
The 74LVT2952 device is an 8-bit registered transceiver. Two 8-bit
back-to-back registers store data flowing in both directions between
two bidirectional buses.
Data applied to the inputs is entered and stored on the rising edge of
the Clock (CPXX) provided that the Clock Enable (CEXX) is LOW.
The data is then present at the 3-State output buffers, but is only
accessible when the Output Enable (OEXX) is LOW. Data flow from
A inputs to B outputs is the same as for B inputs to A outputs.
PIN DESCRIPTION
16, 17, 18,
19, 20, 21,
CC
NUMBER
8, 7, 6, 5,
T
4, 3, 2, 1
amb
10, 14
11, 13
22, 23
9, 15
operation at 3.3 V.
PIN
12
24
CC
= 25 C; GND = 0 V
CONDITIONS
= 3.3 V
I/O
CC
OEAB / OEBA
CEAB / CEBA
CPAB / CPBA
TYPE NUMBER
= 0 V or 3.0 V
= 3.6 V
74LVT2952PW
74LVT2952DB
SYMBOL
74LVT2952D
A0 – A7
B0 – B7
GND
V
CC
Clock input A to B /
Clock input B to A
Clock enable input A to B /
Clock enable input B to A
Data inputs/outputs (A side)
Data outputs/outputs (B side)
Output enable inputs
Ground (0 V)
Positive supply voltage
NAME AND FUNCTION
TYPICAL
74LVT2952
0.13
3.1
3.8
4
8
DWG NUMBER
Product data sheet
SOT137-1
SOT340-1
SOT355-1
853-1765 19918
UNIT
mA
pF
pF
ns