MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 15

• Manufacturer Part Number: MAX5802AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
• Manufacturer: Maxim Integrated

Specifications of MAX5802AAUB+T

• Rohs: yes

The MAX5800/MAX5801/MAX5802 are 2-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a fast 400kHz I
compatible interface. The MAX5800/MAX5801/MAX5802
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) cir-
cuit to initialize the DAC outputs to code zero, and con-
trol logic. CLR is available to asynchronously clear the
device independent of the serial interface.
The MAX5800/MAX5801/MAX5802 include internal buf-
fers on both DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive up to
2kI in parallel with 500pF. The analog supply voltage
(V
of the devices as V
no-load conditions, the output buffers drive from GND to
V
GND, the output buffers drive from GND to within 200mV
of V
from V
The DAC ideal output voltage is defined by:
where D = code loaded into the DAC register, V
reference voltage, N = resolution.
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
Maxim Integrated
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
DD
DD
DD
, subject to offset and gain errors. With a 2kω load to
) determines the maximum output voltage range
DD
. With a 2kω load to V
to within 200mV of GND.
DACs with Internal Reference and I
V
DD
=
OUT
Internal Register Structure
Detailed Description
powers the output buffer. Under
V
REF
DD
DAC Outputs (OUT_)
, the output buffers drive
×
2
D
N
MAX5800/MAX5801/MAX5802
REF
2
C-
=
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zero-
scale defaults.
The MAX5800/MAX5801/MAX5802 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal refer-
ence is selected, that voltage is available on the REF
pin for other external circuitry (see the
Circuits) and can drive a 25kI load.
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to V
supply between REF and GND to apply an exter-
nal
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references
list of available external voltage-reference devices.
The MAX5800/MAX5801/MAX5802 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
both DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I
command, drive CLR high, satisfying the t
requirement.
The MAX5800/MAX5801/MAX5802 feature a separate
supply pin (V
Connect V
reference.
DDIO
DDIO
to the I/O supply of the host processor.
Interface Power Supply (V
) for the digital interface (1.8V to 5.5V).
The
DD
2
C command. To allow a new I
. Connect an external voltage
MAX5800/MAX5801/MAX5802
2
External Reference
Internal Reference
C Interface
Clear Input (CLR)
Typical Operating
CLRSTA
DDIO
timing
for a
2
15
C
)