MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 19

• Manufacturer Part Number: MAX5802AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
• Manufacturer: Maxim Integrated

Specifications of MAX5802AAUB+T

• Rohs: yes

Table 2. Standard I
Figure 6. Standard I
Maxim Integrated
channel CODE register content will be returned; if both
DACs are selected, CODEA content will be returned.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 0001, 0010, or 0011).
For these commands, which support a DAC address, the
requested DAC register content will be returned. If both
DACs are selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[1:0], with a
1 indicating the DAC is powered down and a 0 indicating
the DAC is operational (see
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revi-
sion information in the format as shown in
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
SDA
SCL
0
0
0
0
0
1
1
1
1
START
COMMAND BYTE (REQUEST)
0
0
0
0
1
0
0
0
0
Any other command
0
0
1
1
0
0
0
1
1
0 0 0 1
BYTE #1: I
WRITE ADDRESS
DACs with Internal Reference and I
0
1
0
1
0
0
0
0
1
ADDRESS
2
C Register Read Sequence
2
C SLAVE
1 A1 A0 W A
0
0
0
0
0
DAC selection
DAC selection
DAC selection
DAC selection
2
A
C User Readback Data
0
0
0
0
0
ACK. GENERATED BY MAX5800/MAX5801/ MAX5802
Table
N N N
X
0
0
1
1
BYTE #2: COMMAND 1
WRITE COMMAND 1
2).
X
0
1
0
1
BYTE
N N N N N
0
Table
READBACk DATA HIgH BYTE
0
A
REPEATED
2.
START
MAX5800/MAX5801/MAX5802
0
CODEA[11:4]
CODEn[11:4]
DACn[11:4]
DACn[11:4]
DACn[11:4]
DACA[11:4]
DACA[11:4]
DACA[11:4]
1001 1000
0 0 0 1 1 A1 A0 R A D D D D D D D D
0
BYTE #3: I
READ ADDRESS
ADDRESS
0
While the MAX5800/MAX5801/MAX5802 support stan-
dard I
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, fol-
lowed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5800/
MAX5801/MAX5802. The master still has control of the
2
C SLAVE
0
2
C readback of selected registers, it is also
A
0
ACK. GENERATED BY I
BYTE #4: DATA 1 HIGH
B8
0
BYTE (B[15:8])
READ DATA
B7
0
CODEA[3:0]
CODEn[3:0]
DACn[3:0]
DACn[3:0]
DACn[3:0]
DACA[3:0]
DACA[3:0]
DACA[3:0]
READBACk DATA LOW BYTE
000
B6
2
0
Interface Verification I
C MASTER
A
B5
Readback Operations
0
D D D D D D D D ~A
BYTE #5: DATA 1 LOW
2
C Interface
BYTE (B[7:0])
B4
READ DATA
0
REV_ID[2:0]
(011)
B3
0
0
0
0
0
0
0
0
0
B2
0
0
0
0
0
0
0
0
0
REF MODE
PWB PWA
Figure
B1
0
0
0
0
0
0
0
0
RF[1:0]
STOP
B0
2
0
0
0
0
0
0
0
0
19
C
7.