MAX5802AAUB+T Maxim Integrated, MAX5802AAUB+T Datasheet - Page 16

• Manufacturer Part Number: MAX5802AAUB+T
• Description: Digital to Analog Converters - DAC 12-Bit 2Ch DAC w/I2C
• Manufacturer: Maxim Integrated

Specifications of MAX5802AAUB+T

• Rohs: yes

The MAX5800/MAX5801/MAX5802 feature an I
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5800/
MAX5801/MAX5802 and the master at clock rates up
to 400kHz.
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5800/MAX5801/MAX5802 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5800/
MAX5801/MAX5802 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5800/MAX5801/MAX5802 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5800/
MAX5801/MAX5802 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5800/
MAX5801/MAX5802 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
signals. The MAX5800/MAX5801/MAX5802 can accom-
modate bus voltages higher than V
5.5V; bus voltages lower than V
ed and may result in significantly increased interface cur-
rents. The MAX5800/MAX5801/MAX5802 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can be
loaded without affecting the DAC register(s) using the
write command. To update the DAC registers, use the
software LOAD command.
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SMBus is a trademark of Intel Corp.
Maxim Integrated
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output
Figure 1
I
2
DACs with Internal Reference and I
C START and STOP Conditions
shows the 2-wire interface timing
DDIO
I
2
C Serial Interface
DDIO
are not recommend-
up to a limit of
MAX5800/MAX5801/MAX5802
2
C-/
Figure 2
Figure 2. I
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high
from the master signals the beginning of a transmission
to the MAX5800/MAX5801/MAX5802. The master termi-
nates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
The MAX5800/MAX5801/MAX5802 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. Transmissions ending in an early
STOP condition will not impact the internal device set-
tings. If the STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
will begin transfer of the requested register data from
the beginning (this applies to combined format I
mode transfers only, interface verification mode transfers
will be corrupted). See
SCL
SDA
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
2
P
C START, Repeated START, and STOP Conditions
S
VALID START, REPEATED START, AND STOP PULSES
S
Repeated START Conditions
S
Figure
(Figure
P
Sr
2
2.
I
C Interface
2
C Early STOP and
2). A START condition
P
S
P
P
2
C read
16