CAT64LC40WI-GT3 ON Semiconductor, CAT64LC40WI-GT3 Datasheet - Page 7

• Manufacturer Part Number: CAT64LC40WI-GT3
• Description: EEPROM
• Manufacturer: ON Semiconductor

During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed a
WRITE cycle, the DO pin will output a logical “1” when the
device is deselected. The rising edge of the first “1” input on
the DI pin will reset DO back to the high impedance state
again.
RDY/BUSY
*Please check instruction set table for address.
RDY/BUSY
An alternative to get RDY/BSY status is from the DO pin.
RESET
RESET
DO
SK
CS
DO
SK
CS
DI
DI
1
1
0
0
1
1
0
0
HIGH−Z
HIGH
0
Figure 7. RESET During BUSY Instruction Timing
0
0
1
Figure 8. EWEN Instruction Timing
1
0
1
0
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ADDRESS*
7
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
NOTE: Data may be corrupted if a RESET occurs while the
device is BUSY. If the reset occurs before the BUSY period,
no writing will be initiated. However, if RESET occurs after
the BUSY period, new data will have been written over the
old data.
The WRITE operation can be halted anywhere in the
D15
D0
t
WR