CAT64LC40WI-GT3 ON Semiconductor, CAT64LC40WI-GT3 Datasheet - Page 8
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CAT64LC40WI-GT3
Manufacturer Part Number
CAT64LC40WI-GT3
Description
EEPROM
Manufacturer
ON Semiconductor
Datasheet
1.CAT64LC40WI-GT3.pdf
(12 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CAT64LC40WI-GT3
Manufacturer:
ON/安森美
Quantity:
20 000
Reset
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High−Z
condition.
clear/write cycle, the device will abort the operation and will
display READY status on the RDY/BSY pin and on the DO
pin if CS is low.
WRITEALL operations. It does not reset any other
operations such as READ, EWEN and EWDS.
RDY/BUSY
The RESET pin, when set to HIGH, will reset or abort a
When RESET is set to HIGH, while the device is in a
The RESET input affects only the WRITE and
RESET
CS
DO
SK
DI
1
0
1
0
HIGH−Z
HIGH
0
0
Figure 9. EWDS Instruction Timing
0
0
http://onsemi.com
8
Erase/Write Enable and Disable
state. After power−up or while the device is in an erase/write
disabled state, any write operation must be preceded by an
execution of the EWEN instruction. Once enabled, the
device will stay enabled until an EWDS has been executed
or a power−down has occurred. The EWDS is used to
prevent any inadvertent over−writing of the data. The
EWEN and EWDS instructions have no affect on the READ
operation and are not affected by the RESET input.
The CAT64LC40 powers up in the erase/write disabled