DS28E05R+T Maxim Integrated, DS28E05R+T Datasheet - Page 15
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DS28E05R+T
Manufacturer Part Number
DS28E05R+T
Description
EEPROM 1-Wire 112-BYTE EEPROM
Manufacturer
Maxim Integrated
Datasheet
1.DS28E05PT.pdf
(17 pages)
Specifications of DS28E05R+T
Rohs
yes
DS28E05
The sum of t
timing generator of the DS28E05 on the other side define
the master sampling window (t
which the master must perform a read from the data line.
For the most reliable communication, t
short as permissible, and the master should read close to
but no later than t
line, the master must wait until t
guarantees sufficient recovery time t
to get ready for the next time slot. Note that t
herein applies only to a single DS28E05 attached to a
1-Wire line. For multidevice configurations, t
extended to accommodate the additional 1-Wire device
input capacitance.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to
noise of various origins. Depending on the physical size
and topology of the network, reflections from end points
and branch points can add up or cancel each other to
some extent. Such reflections are visible as glitches or
Table 5. 1-Wire Communication Legend
Table 6. Data Direction Codes
www.maximintegrated.com
Master-to-Slave
<data to EOP>
<n bytes>
SYMBOL
Release
FF loop
Select
Data
RST
WM
RM
PD
PB
CS
RL
+ δ (rise time) on one side and the internal
Slave-to-Master Master waits (1-Wire idle high)
MSR(MAX)
1-Wire reset pulse generated by master
1-Wire presence detect pulse generated by slave
Command and data to satisfy the ROM function protocol
Parameter byte
Command Success indicator
FFh byte sent by the master to start a write activity in the slave
Command “Write Memory”
Command “Read Memory”
Transfer of n bytes
Transfer of as many bytes as are needed to reach the end of the page
Transfer of 2 bytes segment data
Indefinite loop where the bus master reads FFh bytes
. After reading from the data
MSR(MIN)
SLOT
REC
RL
to t
for the DS28E05
is expired. This
MSR(MAX)
REC
should be as
REC
specified
must be
), in
Figure 11. Noise Suppression Scheme
ringing on the 1-Wire communication line. Noise coupled
onto the 1-Wire line from external sources can also result
in signal glitching. A glitch during the rising edge of a time
slot can cause a slave device to lose synchronization
with the master and, consequently, result in a Search
ROM command coming to a dead end or cause a device-
specific function command to abort. The DS28E05 uses a
1-Wire front-end with built-in hysteresis at the low-to-high
switching threshold V
but does not go below V
1-Wire Communication Examples
See
legend and data direction codes.
DESCRIPTION
Table 5
V
PUP
V
V
0V
TH
TL
and
V
HY
Table 6
TH
TL
. If a negative glitch crosses V
, it is not recognized (Figure 11).
for the 1-Wire communication
1-Wire EEPROM
Maxim Integrated │ 15
TH