DS28E05R+T Maxim Integrated, DS28E05R+T Datasheet - Page 4
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DS28E05R+T
Manufacturer Part Number
DS28E05R+T
Description
EEPROM 1-Wire 112-BYTE EEPROM
Manufacturer
Maxim Integrated
Datasheet
1.DS28E05PT.pdf
(17 pages)
Specifications of DS28E05R+T
Rohs
yes
DS28E05
Pin Configurations
Pin Descriptions
Detailed Description
The DS28E05 combines 896 bits of user EEPROM orga-
nized as seven 128-bit pages, 64 bits of administrative
data memory, and a 64-bit ROM ID in a single chip. Data
is transferred serially through the 1-Wire protocol, which
requires only a single data lead and a ground return.
The user memory can have unrestricted write access (fac-
tory default), or can be write protected or put in EPROM
emulation mode. Write protection prevents changes to
the memory data. EPROM emulation mode logically
ANDs memory data with incoming new data, which allows
changing bits from 1 to 0, but not vice versa. By chang-
ing one bit at a time this mode could be used to create
nonvolatile nonresettable counters. For more details
refer to
Nonresettable Counters for Embedded
The device’s 64-bit ROM ID can be used to electronically
identify the equipment in which the DS28E05 is used.
The ROM ID guarantees unique identification and is also
used to address the device in a multidrop 1-Wire network
environment, where multiple devices reside on a com-
mon 1-Wire bus and operate independently of each other.
Applications include accessory/PCB identification, medi-
cal sensor calibration data storage, analog sensor calibra-
tion, and after-market management of consumables.
www.maximintegrated.com
SOT23
2
1
3
Application Note 5042: Implementing Nonvolatile,
PIN
TSOC
3–6
2
1
TOP VIEW
N.C.
NAME
GND
IO
N.C.
IO
1
2
+
DS28E05
SOT23
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Ground Reference
Systems.
3 GND
Overview
The block diagram in
between the major control and memory sections of the
DS28E05. The DS28E05 has three main data compo-
nents: seven 128-bit pages of user EEPROM, 64 bits
of administrative data memory, and a 64-bit ROM ID.
Figure 2
protocol. The bus master must first provide one of the
five ROM function commands: Read ROM, Match ROM,
Search ROM, Skip ROM, or Resume Communication.
The protocol required for these ROM function commands
is described in Figure 8. After a ROM function command
is successfully executed, the memory functions become
accessible and the master can select one of the two
memory function commands. The function protocols are
described in Figure 6. All data is read and written least
significant bit first.
64-Bit ROM ID
Each DS28E05 contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a
cyclic redundancy check (CRC) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using
a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4.
TOP VIEW
GND
N.C.
IO
shows the hierarchic structure of the 1-Wire
FUNCTION
1
2
3
+
DS28E05
TSOC
Figure 1
6
5
4
N.C.
N.C.
N.C.
1-Wire EEPROM
shows the relationships
Maxim Integrated │ 4