CAT25512YI-GT3 ON Semiconductor, CAT25512YI-GT3 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/4/495/on_semiconductor_sml.jpg)
CAT25512YI-GT3
Manufacturer Part Number
CAT25512YI-GT3
Description
EEPROM
Manufacturer
ON Semiconductor
Datasheet
1.CAT25512YI-GT3.pdf
(16 pages)
Specifications of CAT25512YI-GT3
Rohs
yes
Memory Size
512 KB
Organization
64 K x 8
Data Retention
100 yr
Maximum Clock Frequency
20 MHz
Maximum Operating Current
2 mA
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 130 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
The CAT25512 device powers up into a write disable
SCK
SO
CS
SCK
SI
SO
CS
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
0
0
Figure 3. WREN Timing
WRITE OPERATIONS
0
0
Figure 4. WRDI Timing
http://onsemi.com
0
0
HIGH IMPEDANCE
0
0
HIGH IMPEDANCE
6
0
0
Write Enable and Write Disable
Status Register WEL bit are set by sending the WREN
instruction to the CAT25512. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
1
The internal Write Enable Latch and the corresponding
The internal write enable latch is reset by sending the
1
1
0
0
0