CAT25512YI-GT3 ON Semiconductor, CAT25512YI-GT3 Datasheet - Page 7

• Manufacturer Part Number: CAT25512YI-GT3
• Description: EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAT25512YI-GT3

• Rohs: yes
• Memory Size: 512 KB
• Organization: 64 K x 8
• Data Retention: 100 yr
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 130 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8

Byte Write
sequence, by sending a WRITE instruction, a 16−bit address
and a data byte as shown in Figure 5. Internal programming
will start after the low to high CS transition. During an
internal write cycle, all commands, except for RDSR (Read
Status Register) will be ignored. The RDY bit will indicate
if the internal write cycle is in progress (RDY high), or the
device is ready to accept commands (RDY low).
Page Write
may continue sending data, up to a total of 128 bytes,
according to timing shown in Figure 6. After each data byte,
the lower order address bits are automatically incremented,
while the higher order address bits (page address) remain
unchanged. If during this process the end of page is
exceeded, then loading will “roll over” to the first byte in the
page, thus possibly overwriting previously loaded data.
Table 11. BYTE ADDRESS
Main Memory Array
Identification Page
Once the WEL bit is set, the user may execute a write
After sending the first data byte to the CAT25512, the host
SCK
SCK
SO
CS
SO
CS
SI
SI
Dashed Line = mode (1, 1)
Dashed Line = mode (1, 1)
Device
0
0
0
0
0
0
1
1
0
0
2
HIGH IMPEDANCE
2
0
0
3
3
OPCODE
OPCODE
0
0
4
4
Address Significant Bits
0
0
5
5
1
1
A15 − A0
6
6
A6 − A0
0
0
Figure 6. Page WRITE Timing
Figure 5. Byte WRITE Timing
7
7
A
A
N
8
N
8
BYTE ADDRESS*
http://onsemi.com
BYTE ADDRESS*
HIGH IMPEDANCE
21 22 23 24 25 26 27
21 22 23 24−31 32−39
7
Following completion of the write cycle, the CAT25512 is
automatically returned to the write disable state.
Write Identification Page
written with user data using the same Write commands
sequence as used for Page Write to the main memory array
(Figure 6). The IPL bit from the Status Register must be set
(IPL = 1) using the WRSR instruction, before attempting
to write to the IP.
[A6:A0] bits define the byte address within the
Identification Page. In addition, the Byte Address must point
to a location outside the protected area defined by the BP1,
BP0 bits from the Status Register. When the full memory
array is write protected (BP1, BP0 = 1,1), the write
instruction to the IP is not accepted and not executed.
the Status Register is set to 1 (the page is locked in
Read−only mode).
# Address Clock Pulses
A
A
The additional 128−byte Identification Page (IP) can be
The address bits [A15:A7] are Don’t Care and the
Also, the write to the IP is not accepted if the LIP bit from
0
0
Byte 1
D7 D6 D5 D4 D3 D2 D1 D0
Data
* Please check the Byte Address Table (Table 11)
* Please check the Byte Address Table (Table 11)
Byte 2
16
16
Data
DATA IN
Byte 3
DATA IN
24+(N−1)x8−1 .. 24+(N−1)x8
Data
28
Data Byte N
7..1
29 30 31
0
24+Nx8−1