CAT25512YI-GT3 ON Semiconductor, CAT25512YI-GT3 Datasheet - Page 8

• Manufacturer Part Number: CAT25512YI-GT3
• Description: EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAT25512YI-GT3

• Rohs: yes
• Memory Size: 512 KB
• Organization: 64 K x 8
• Data Retention: 100 yr
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Current: 2 mA
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 130 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8

Write Status Register
instruction according to timing shown in Figure 7. Only bits
2, 3, 4, 6 and 7 can be written using the WRSR command.
the low to high CS transition. The internal write cycle will
last maximum 5 ms (t
RDSR) while writing to the status register is in progress
and insert a fixed delay of 5 ms before sending any other
instruction to the CAT25512.
SCK
SO
CS
The Status Register is written by sending a WRSR
The internal programming for the SR bits will start after
It is recommended to avoid SR polling routine (through
SI
Dashed Line = mode (1, 1)
SCK
WP
WP
CS
Dashed Line = mode (1, 1)
0
0
0
1
WC
).
HIGH IMPEDANCE
0
2
0
3
OPCODE
0
4
0
5
Figure 7. WRSR Timing
Figure 8. WP Timing
0
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6
1
7
8
t
MSB
WPS
8
7
Write Protection
Block Protect bits BP0 and BP1 against being inadvertently
altered. When WP is low and the WPEN bit is set to “1”,
write operations to the Status Register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any write
operation to the Status Register. The WP pin function is
blocked when the WPEN bit is set to “0”. The WP input
timing is shown in Figure 8.
The Write Protect (WP) pin can be used to protect the
t
9
6
WPH
10
5
11
4
DATA IN
12
3
13
2
14
1
15
0