M95040-RMC6TG STMicroelectronics, M95040-RMC6TG Datasheet - Page 11

• Manufacturer Part Number: M95040-RMC6TG
• Description: EEPROM 4 Kbit SPI BUS EE 10MHz CR 5ms
• Manufacturer: STMicroelectronics

Specifications of M95040-RMC6TG

• Product Category: EEPROM
• Rohs: yes

M950x0 M950x0-W M950x0-R
3
Connecting to the SPI bus
The device is fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3: Bus master and memory devices on the SPI bus
memory devices connected to an MCU, on an SPI bus. Only one memory device is selected
at a time, so only one memory device drives the Serial Data output (Q) line at a time, the
other memory devices are high impedance.
The pull-up resistor R (represented in
bus) ensures that a device is not selected if the bus master leaves the S line in the high
impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
the transmission of an Instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the t
Figure 3.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
CS3
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus master
CS2 CS1
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
SHCH
C Q D
S
requirement is met. The typical value of R is 100 k .
SPI mmory
Doc ID 6512 Rev 10
device
W
V
Figure 3: Bus master and memory devices on the SPI
CC
HOLD
V
SS
R
C Q D
S
SPI memory
device
W
shows an example of three
V
HOLD
CC
Connecting to the SPI bus
V
SS
R
C Q D
S
SPI memory
device
W
V
CC
HOLD
AI12304b
V
11/44
SS
V
V
CC
SS