M95128-DFMN6TP STMicroelectronics, M95128-DFMN6TP Datasheet - Page 17

• Manufacturer Part Number: M95128-DFMN6TP
• Description: EEPROM Automotive 128kBit SPI High Speed Clock
• Manufacturer: STMicroelectronics

Specifications of M95128-DFMN6TP

• Rohs: yes

M95128-W M95128-R M95128-DF
6.1
6.2
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8.
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Enable (WREN) sequence
Figure
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven low,
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 5798 Rev 16
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI02281E
Instructions
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