M95128-DFDW6TP STMicroelectronics, M95128-DFDW6TP Datasheet - Page 19

• Manufacturer Part Number: M95128-DFDW6TP
• Description: EEPROM Automotive 128kBit SPI High Speed Clock
• Manufacturer: STMicroelectronics

Specifications of M95128-DFDW6TP

• Rohs: yes

M95128-W M95128-R M95128-DF
6.3.2
6.3.3
6.3.4
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
●
●
●
●
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 6.
Status Register Write Protect
SRWD
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
b7
Status Register format
0
0
Doc ID 5798 Rev 16
0
Table
BP1
2) becomes protected against Write
Block Protect bits
Write Enable Latch bit
BP0
WEL
Write In Progress bit
Instructions
WIP
b0
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