M24C32-DFMC6TG STMicroelectronics, M24C32-DFMC6TG Datasheet - Page 18
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M24C32-DFMC6TG
Manufacturer Part Number
M24C32-DFMC6TG
Description
EEPROM 32 Kbit I2C EEProm 4kB 2.5V to 5.5V
Manufacturer
STMicroelectronics
Datasheet
1.M24C32-FDW6TP.pdf
(40 pages)
Specifications of M24C32-DFMC6TG
Rohs
yes
Instructions
5.1.5
18/40
ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the
I
The ECC logic is implemented on each group of four EEPROM bytes
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in
a.
2
C communication protocol.
A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an
integer.
Doc ID 4578 Rev 21
M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF
Table 12: Cycling performance by groups of four
(a)
. As a consequence, the maximum cycling budget is
(a)
. Inside a group, if a
bytes.