LCMXO2-256HC-4SG32I Lattice, LCMXO2-256HC-4SG32I Datasheet - Page 25

• Manufacturer Part Number: LCMXO2-256HC-4SG32I
• Description: FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 3.3V -6 Speed
• Manufacturer: Lattice

Specifications of LCMXO2-256HC-4SG32I

• Rohs: yes
• Number Of I/os: 22
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Distributed Ram: 2 KB
• Operating Supply Current: 18 uA
• Factory Pack Quantity: 490

Figure 2-17. Output Gearbox
More information on the output gearbox is available in TN1203,
MachXO2
DDR Memory Support
Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry
to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right
edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up
to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write
D6
D4
D2
D0
D1
D3
D5
D7
Devices.
ODDRx2_C
ODDRx2_A
ODDRx2_C
SCLK
SEL /0
UPDATE
ECLK0/1
Q
D Q
D Q
Q
D Q
D Q
D Q
D Q
CDN
D
D
T6
T4
T2
T0
T1
T3
T5
T7
CE
CE
CE
CE
D Q
CE
D Q
CE
D Q
CE
D Q
D Q
D Q
D Q
D Q
CE
S6
S4
S2
S0
S1
S3
S5
S7
S7
S5
S3
S1
S0
S2
S4
S6
2-21
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GND
Q67
Q45
Q23
Q12
Q34
Q56
GND
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Implementing High-Speed Interfaces with
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
MachXO2 Family Data Sheet
Q67
Q45
Q23
Q01
Q10
Q32
Q54
Q76
Architecture
QC
Q/QA