LCMXO2-256HC-4SG32I Lattice, LCMXO2-256HC-4SG32I Datasheet - Page 32

• Manufacturer Part Number: LCMXO2-256HC-4SG32I
• Description: FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 3.3V -6 Speed
• Manufacturer: Lattice

Specifications of LCMXO2-256HC-4SG32I

• Rohs: yes
• Number Of I/os: 22
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Distributed Ram: 2 KB
• Operating Supply Current: 18 uA
• Factory Pack Quantity: 490

Figure 2-20. Embedded Function Block Interface
Hardened I
Every MachXO2 device contains two I
two cores can be configured either as an I
cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I
face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I
The I
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 KHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
2
C cores support the following functionality:
2
C IP Core
Routing
Logic/
Core
WISHBONE
Interface
PLL0
2
EFB
Configuration
C IP cores. These are the primary and secondary I
Embedded Function Block (EFB)
Logic
2
C master or as an I
PLL1
I
2
Timer/Counter
I
C (Secondary)
2-28
2
C (Primary)
Control
SPI
Power
2
UFM
C slave. The only difference between the two IP
MachXO2 Family Data Sheet
Indicates connection
through core logic/routing.
(Secondary)
I/Os for I
I/Os for I
I/Os for SPI
(Primary)
2
2
C
C
2
2
C IP cores. Either of the
C bus through the inter-
Architecture
2
C Master.