LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 32
LCMXO2-1200ZE-1UWG25ITR50
Manufacturer Part Number
LCMXO2-1200ZE-1UWG25ITR50
Description
FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
Manufacturer
Lattice
Datasheet
1.LCMXO2-256HC-4SG32I.pdf
(106 pages)
Specifications of LCMXO2-1200ZE-1UWG25ITR50
Rohs
yes
Number Of Gates
1200
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
19
Maximum Operating Frequency
400 MHz
Operating Supply Voltage
1.2 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Package / Case
WLCPS-25
Distributed Ram
10 Kbit
Operating Supply Current
56 uA
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Figure 2-20. Embedded Function Block Interface
Hardened I
Every MachXO2 device contains two I
two cores can be configured either as an I
cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.
When the IP core is configured as a master it will be able to control other devices on the I
face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I
The I
• Master and Slave operation
• 7-bit and 10-bit addressing
• Multi-master arbitration support
• Clock stretching
• Up to 400 KHz data transfer speed
• General call support
• Interface to custom logic through 8-bit WISHBONE interface
2
C cores support the following functionality:
2
C IP Core
Routing
Logic/
Core
WISHBONE
Interface
PLL0
2
EFB
Configuration
C IP cores. These are the primary and secondary I
Embedded Function Block (EFB)
Logic
2
C master or as an I
PLL1
I
2
Timer/Counter
I
C (Secondary)
2-28
2
C (Primary)
Control
SPI
Power
2
UFM
C slave. The only difference between the two IP
MachXO2 Family Data Sheet
Indicates connection
through core logic/routing.
(Secondary)
I/Os for I
I/Os for I
I/Os for SPI
(Primary)
2
2
C
C
2
2
C IP cores. Either of the
C bus through the inter-
Architecture
2
C Master.
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