LCMXO2-1200ZE-1UWG25ITR50 Lattice, LCMXO2-1200ZE-1UWG25ITR50 Datasheet - Page 79

• Manufacturer Part Number: LCMXO2-1200ZE-1UWG25ITR50
• Description: FPGA - Field Programmable Gate Array 19 LUTs 19 IO 1.2V 1 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1UWG25ITR50

• Rohs: yes
• Number Of Gates: 1200
• Embedded Block Ram - Ebr: 64 Kbit
• Number Of I/os: 19
• Maximum Operating Frequency: 400 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: WLCPS-25
• Distributed Ram: 10 Kbit
• Operating Supply Current: 56 uA

Pin Information Summary
General Purpose I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Single Ended
I/O
Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Total General Purpose Differential I/O
Dual Function I/O
High-speed Differential I/O
Bank 0
Gearboxes
Number of 7:1 or 8:1 Output Gearbox
Available (Bank 0)
Number of 7:1 or 8:1 Input Gearbox
Available (Bank 2)
DQS Groups
Bank 1
VCCIO Pins
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
VCC
GND
NC
Total Count of Bonded Pins
1. Lattice recommends soldering the central thermal pad onto the top PCB ground for improved thermal resistance.
32 QFN
21
10
22
31
8
2
9
2
0
0
4
1
4
1
0
0
0
0
0
0
2
1
2
1
0
0
2
2
0
1
64 ucBGA 100 TQFP 132 csBGA 100 TQFP 132 csBGA
12
11
12
22
44
27
62
9
0
0
5
6
5
6
0
0
0
0
0
0
2
2
2
2
0
0
2
8
1
MachXO2-256
4-3
13
14
14
14
55
28
29
26
73
0
0
7
7
7
7
0
0
0
0
0
0
2
2
2
2
0
0
2
8
13
14
14
14
55
28
29
58
73
0
0
7
7
7
7
0
0
0
0
0
0
2
2
2
2
0
0
2
8
MachXO2 Family Data Sheet
18
20
20
20
78
10
10
10
39
29
96
MachXO2-640
0
0
9
0
0
0
0
0
0
2
2
2
2
0
0
2
8
3
Pinout Information
19
20
20
20
79
10
10
10
10
40
29
10
32
99
0
0
0
0
0
0
0
0
2
2
2
2
0
0
2
MachXO2-640U
144 TQFP
107
135
54
27
26
28
26
14
13
14
13
33
12
0
0
0
0
7
7
7
2
3
3
3
3
0
0
4
8