iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 12

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
the level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to
ensure that all V
the I/O banks that are critical to the application. The default configuration of the I/O pins in a device prior to config-
uration is tri-stated with a weak pull-up to V
V
ware user-configured settings only after a proper download/configuration. Unused IOs are automatically blocked
and the pullup termination is disabled.
Supported Standards
The iCE40 sysIO buffer supports both single-ended and differential input standards. The single-ended standard
supported is LVCMOS. The buffer supports the LVCMOS 1.8, 2.5, and 3.3V standards. The buffer has individually
configurable options for bus maintenance (weak pull-up or none).
Table 2-7 and Table 2-8 show the I/O standards (together with their supply and reference voltages) supported by
the iCE40 devices.
Table 2-7. Supported Input Standards
Table 2-8. Supported Output Standards
Non-Volatile Configuration Memory
All iCE40 devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure the
device.
For more information on the NVCM, please refer to TN1248,
CCIO
(for I/O banks containing configuration I/Os) have reached levels, at which time the I/Os will take on the soft-
Single-Ended Interfaces
LVCMOS33
LVCMOS25
LVCMOS18
Differential Interfaces
LVDS25E
subLVDSE
1. These interfaces can be emulated with external resistors in all devices.
Single-Ended Interfaces
LVCMOS33
LVCMOS25
LVCMOS18
Differential Interfaces
LVDS25
subLVDS
1. Bank 3 only.
CCIO
1
1
1
banks are active with valid input logic levels to properly control the output logic states of all
1
Output Standard
Input Standard
CCIO
. The I/O pins will maintain the pre-configuration state until V
3.3V
2-9

iCE40 Programming and Configuration Usage
CC
, V
V
V
CCIO
CCIO_2
CCIO
2.5V
iCE40 LP/HX Family Data Sheet
(Typical)


3.3
2.5
1.8
2.5
1.8
(Typical)
, V
PP_2V5
, and V
1.8V


CC_SPI
Architecture
have reached
CC
Guide.
and