iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 5

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

PLB Blocks
The core of the iCE40 device consists of Programmable Logic Blocks (PLB) which can be programmed to perform
logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in Figure 2-2.
Each LC contains one LUT and one register.
Figure 2-2. PLB Block Diagram
Logic Cells
Each Logic Cell includes three primary logic elements shown in Figure 2-2.
Table 2-1. Logic Cell Signal Descriptions
1. If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.
Function
• A four-input Look-Up Table (LUT4) builds any combinational logic function, of any complexity, requiring up to
• A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic func-
• Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,
Output
Output
Input
Input
Input
Input
Input
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory (ROM). Combine and cas-
cade multiple LUT4s to create wider logic functions.
tions. Each DFF also connects to a global reset signal that is automatically asserted immediately following
device configuration.
comparators, binary counters and some wide, cascaded logic functions.
Data signal
Control signal
Control signal
Control signal
Data signals
Inter-PFU signal
Inter-PLB signal
Type
Programmable Logic
Block (PLB)
Signal Names
I0, I1, I2, I3
Set/Reset
FCOUT
Enable
Clock
FCIN
O
= Statically defined by configuration program
I0
I1
I2
I3
FCOUT
1
FCIN
Four-input
Look-Up Table
(LUT4)
Carry Logic
Inputs to LUT4
Clock enable shared by all LCs in the PLB
Asynchronous or synchronous local set/reset shared by all LCs in
the PLB.
Clock one of the eight Global Buffers, or from the general-purpose
interconnects fabric shared by all LCs in the PLB
Fast carry in
LUT4 or registered output
Fast carry out
Shared Block-Level Controls
Set/Reset
2-2
Enable
Clock
LUT4
0
1
iCE40 LP/HX Family Data Sheet
Flip-flop with
optional enable and
set or reset controls
D
EN
Description
DFF
SR
Logic Cell
Q
O
Architecture