OR2C08A3M84I-D Lattice, OR2C08A3M84I-D Datasheet - Page 2

• Manufacturer Part Number: OR2C08A3M84I-D
• Description: FPGA - Field Programmable Gate Array Use ECP/EC or XP LatticeXP
• Manufacturer: Lattice

Specifications of OR2C08A3M84I-D

• Product Category: FPGA - Field Programmable Gate Array
• Number Of Gates: 21.6 K
• Number Of I/os: 224
• Maximum Operating Frequency: 40 MHz
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: OR2C-84
• Minimum Operating Temperature: - 40 C

ORCA Series 2 FPGAs
Description
The ORCA Series 2 series of SRAM-based FPGAs are
an enhanced version of the ATT2C/2T architecture.
The latest ORCA series includes patented architectural
enhancements that make functions faster and easier to
design while conserving the use of PLCs and routing
resources.
The Series 2 devices can be used as drop-in replace-
ments for the ATT2Cxx/ATT2Txx series, respectively,
and they are also bit stream compatible with each
other. The usable gate counts associated with each
series are provided in Table 1. All devices are offered in
a variety of packages, speed grades, and temperature
ranges.
ORCA FPGAs consist of two basic elements: program-
mable logic cells (PLCs) and programmable input/out-
put cells (PICs). An array of PLCs is surrounded by
PICs as shown in Figure 1. Each PLC contains a pro-
grammable function unit (PFU). The PLCs and PICs
also contain routing resources and configuration RAM.
All logic is done in the PFU. Each PFU contains four
16-bit look-up tables (LUTs) and four latches/flip-flops
(FFs).
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can be programmed to real-
2 2
WD[3:0]
CKEN
GSR
LSR
CIN
TRI
CK
C0
A4
A3
A2
A1
A0
B4
B3
B2
B1
B0
A4
A3
A2
A1
A3
A2
A1
A0
B4
B3
B2
B1
B3
B2
B1
B0
QLUT3
QLUT2
QLUT1
QLUT0
CARRY
CARRY
CARRY
CARRY
A4
B4
Figure 1. PFU Block Diagram
PFU_NAND
PFU_MUX
PFU_XOR
C
C
C
C
C
C
F3
F2
F1
F0
WD3
WD2
WD1
WD0
ize any four-, five-, or six-input logic functions. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, the multiplier function, or the enhanced data
path functions. In memory mode, the LUTs can be
used as a 16 x 4 read/write or read-only memory
(asynchronous mode or synchronous mode) or a 16 x
2 dual-port memory.
The PLC architecture provides a balanced mix of logic
and routing that allows a higher utilized gate/PFU than
alternative architectures. The routing resources carry
logic signals between PFUs and I/O pads. The routing
in the PLC is symmetrical about the horizontal and ver-
tical axes. This improves routability by allowing a bus of
signals to be routed into the PLC from any direction.
Each PIC (shown in Figures 2A and 2B) is comprised
of I/O drivers, I/O pads, and routing resources. Each
I/O can be programmed to be either an input, output, or
bidirectional signal. Other options include variable out-
put slew rates and pull-up or pull-down resistors.
OR2TxxA and OR2TxxB I/Os are 5 V tolerant to allow
interconnection to both 3.3 V and 5 V devices, select-
able on a per-pin basis.
D3
D2
D1
D0
C
SR
SR
SR
SR
REG3
REG2
REG1
REG0
EN
EN
EN
EN
C
Q3
Q2
Q1
Q0
C
T
T
T
T
C
COUT
O4
O3
O2
O1
O0
Lattice Semiconductor
C
T
T
T
T
December 2005
Product Brief
5-4573(F)