W5100 WIZnet, W5100 Datasheet - Page 22

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W5100

Manufacturer Part Number
W5100
Description
Ethernet ICs 3-IN-1 ENET CONTR TCP/IP+MAC+PHY
Manufacturer
WIZnet
Datasheet

Specifications of W5100

Rohs
yes
Product
Ethernet Controllers
Data Rate
10 Mb/s, 100 Mb/s
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 80 C
Package / Case
LQFP-80
Ethernet Connection Type
10Base-T, 100Base-TX
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Standard Supported
802.3, 802.3u

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© Copyright 2009-2010 WIZnet Co., Inc. All rights reserved.
IR (Interrupt Register) [R] [0x0015] [0x00]
This register is accessed by the host processor to know the cause of an interrupt.
Any interrupt can be masked in the Interrupt Mask Register (IMR). The /INT signal retain low
as long as any masked signal is set, and will not go high until all masked bits in this Register
have been cleared.
CONFLICT
Bit
7
6
4
3
2
1
5
7
CONFLICT
UNREACH
Reserved
Symbol
S3_INT
S2_INT
S1_INT
PPPoE
UNREACH
6
IP Conflict
It is set as „1‟, when there is ARP request with same IP address as Source IP
address. This bit is cleared to „0‟ by writing „1‟ to this bit.
Destination unreachable
W5100 will receive ICMP(Destination Unreachable) packet if non-existing
destination IP address is transmitted during UDP data transmission. (Refer
to “5.2.2 UDP”). In this case, the IP address and the port number will be
saved in Unreachable IP Address (UIPR) and Unreachable Port Register
(UPORT), and the bit will be set as „1‟. This bit will be cleared to „0‟ by
writing „1‟ to this bit.
PPPoE Connection Close
In the PPPoE Mode, if the PPPoE connection is closed, „1‟ is set. This bit
will be cleared to „0‟ by writing „1‟ to this bit.
Reserved
Occurrence of Socket 3 Socket Interrupt
It is set in case that interrupt occurs at the socket 3. For more detailed
information of socket interrupt, refer to “Socket 3 Interrupt Register
(S3_IR)”. This bit will be automatically cleared when S3_IR is cleared to
0x00.
Occurrence of Socket 2 Socket Interrupt
It is set in case that interrupt occurs at the socket 2. For more detailed
information
Register(S2_IR)”. This bit will be automatically cleared when S2_IR is
cleared to 0x00.
Occurrence of Socket 1 Socket Interrupt
It is set in case that interrupt occurs at the socket 1. For more detailed
information of socket interrupt, refer to “Socket 1 Interrupt Register
PPPoE
5
of
Reserved
socket
4
interrupt,
Description
S3_INT
3
refer
S2_INT
2
to
“Socket
S1_INT
1
2
Interrupt
S0_INT
0
22

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