W3150A+ WIZnet, W3150A+ Datasheet - Page 56
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W3150A+
Manufacturer Part Number
W3150A+
Description
Ethernet ICs ENET CONTR TCP/IP+MAC
Manufacturer
WIZnet
Datasheet
1.W3150A.pdf
(67 pages)
Specifications of W3150A+
Rohs
yes
Product
Ethernet Transceivers
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 80 C
Package / Case
LQFP-64
Ethernet Connection Type
10Base-T, 100Base-TX
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
▪ 6.3.1 Device Operation
The W3150A+ is controlled by a set of instruntion that is sent from a host controller, commonly referred to
as the SPI Master. The SPI Master communicates with W3150A+ via the SPI bus which is composed of four
signal lines: Slave Select(/SS), Serial Clock(SCLK), MOSI(Master Out Slave In), MISO(Master In Slave Out).
The SPI protocol defines four modes for its operation (Mode 0, 1, 2, 3). Each mode differs according to the
SCLK polarity and phase - how the polarity and phase control the flow of data on the SPI bus.
The W3150A+ is SPI Slave device and supports the most common modes - SPI Mode 0 and 3.
The only difference between SPI Mode 0 and 3 is the polarity of the SCLK signal at the inactive state. With
SPI Mode 0 and 3, data is always latched in on the rising edge of SCLK and always output on the falling
edge of SCLK.
▪ 6.3.2 Commands
According to SPI protocol, there are only two data lines between SPI devices. So, it is necessary to define
OP-Code. W3150A+ uses two kinds of OP-Code, Read OP-Code and Write OP-Code. Except for those two
OP-Codes, W3150A+ will be ignored and no operation will be started.
In SPI Mode, W3150A+ operates in “unit of 32-bit stream”.
The unit of 32-bit stream is composed of 1 byte OP-Code Field, 2 bytes Address Field and 1 byte data Field.
OP-Code, Address and data bytes are transferred with the most significant bit(MSB) first and least
significant bit(LSB) last. In other words, The first bit of SPI data is MSB of OP-Code Field and the last bit of
SPI data is LSB of Data-Field. W3150A+ SPI data format is as below.
▪ 6.3.3 Process of using general SPI Master device (According to SPI protocol)
▫ 1. Configure Input/Output direction on SPI Master device pins.
▫ 2. Configure /SS as ‘High’
▫ 3. Configure the registers on SPI Master device.
Write operation
Read operation
* /SS (Slave Select) : Output pin
* SCLK (Serial Clock) : Output pin
* MOSI (Master Out Slave In) : Output pin
* MISO (Master In Slave Out) : Input pin)
* SPI Enable bit on SPCR register (SPI Control Register)
* Master/Slave select bit on SPCR register
* SPI Mode bit on SPCR register
* SPI data rate bit on SPCR register ans SPSR register (SPI State Register)
Command
© Copyright 2006 WIZnet Co., Inc. All rights reserved.
0xF0
0x0F
OP-Code Field
1111 0000
0000 1111
- 55 -
Address Field
2 bytes
2 bytes
Data Field
1 byte
1 byte