1893CKLFT IDT, 1893CKLFT Datasheet
1893CKLFT
Specifications of 1893CKLFT
Related parts for 1893CKLFT
1893CKLFT Summary of contents
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... Set Interface ICS1893CK-40, Rev. C, 06/02/09 IDT reserves the right to make changes in the device data identified in this publication without further notice. IDT advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ...
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ICS1893CK-40 Data Sheet - Release Revision History • Initial preliminary release of this document, Rev. A, dated October 2, 2007. • Rev B; removed all references to CRS and COL; removed AMDIX_EN (pin 10) and all references. • Rev C; ...
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ICS1893CK-40 Data Sheet Rev Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI ...
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ICS1893CK-40 Data Sheet - Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OSI Open Systems Interconnection OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY physical-layer device The ICS1893CK- physical-layer device, also referred ...
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ICS1893CK-40 Data Sheet Rev Release Chapter 2 Conventions and Nomenclature Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet. Table 2-1. Conventions and Nomenclature Item Bits Code groups Colon (:) Numbers Pin (or ...
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ICS1893CK-40 Data Sheet - Release Table 2-1. Conventions and Nomenclature (Continued) Item Signal references Symbols Terms: ‘set’, ‘active’, ‘asserted’, Terms: ‘cleared’, ‘de-asserted’, ‘inactive’ Terms: ‘twisted-pair receiver’ Terms: ‘twisted-pair transmitter’ ICS1893CK-40, Rev. C, 06/02/09 Convention / Nomenclature • When referring to ...
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ICS1893CK-40 Data Sheet Rev Release Chapter 3 Overview of the ICS1893CK-40 The ICS1893CK- stream processor. During data transmission, it accepts sequential nibbles from its MAC (Media Access Control) converts them into a serial bit stream, encodes ...
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ICS1893CK-40 Data Sheet - Release 3.1 100Base-TX Operation During 100Base-TX data transmission, the ICS1893CK-40 accepts packets from a MAC and inserts Start-of-Stream Delimiters (SSDs) and End-of-Stream Delimiters (ESDs) into the data stream. The ICS1893CK-40 encapsulates each MAC frame, including the ...
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ICS1893CK-40 Data Sheet Rev Release Chapter 4 Operating Modes Overview The ICS1893CK-40 operating modes are typically controlled from software. The ICS1893CK-40 register bits are accessible through a standard MII (Media Independent Interface) Serial Management Port. The ICS1893CK-40 is ...
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ICS1893CK-40 Data Sheet - Release 4.1 Reset Operations This section first discusses reset operations in general and then specific ways in which the ICS1893CK-40 can be configured for various reset options. 4.1.1 General Reset Operations The following reset operations apply ...
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ICS1893CK-40 Data Sheet Rev Release 4.1.2 Specific Reset Operations This section discusses the following specific ways that the ICS1893CK-40 can be reset: • Hardware reset (using the RESETn pin) • Power-on reset (applying power to the ICS1893CK-40) • ...
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ICS1893CK-40 Data Sheet - Release 4.1.2.3 Software Reset Entering Software Reset Initiation of a software reset occurs when a management entity writes a logic one to Control Register bit 0.15. When this write occurs, the ICS1893CK-40 enters the reset state ...
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ICS1893CK-40 Data Sheet Rev Release 4.3 Automatic Power-Saving Operations The ICS1893CK-40 has power-saving features that automatically minimize its total power consumption while it is operating. Table 4-1 modes. Table 4-1. Automatic Power-Saving Features, 10Base-T and 100Base-TX Modes Power- ...
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ICS1893CK-40 Data Sheet - Release 4.5 100Base-TX Operations The ICS1893CK-40 100Base-TX mode provides 100Base-TX physical layer (PHY) services as defined in the ISO/IEC 8802-3 standard. In the 100Base-TX mode, the ICS1893CK- 100M translator between a MAC and the ...
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ICS1893CK-40 Data Sheet Rev Release 4.8 Auto-MDI/MDIX Crossover (New) The ICS1893CK-40 includes the auto-MDI/MDIX crossover feature typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the ...
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ICS1893CK-40 Data Sheet - Release Chapter 5 Interface Overviews The ICS1893CK-40 MAC Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC-to-PHY interfaces: • Section 5.1, “MII Data Interface” • ...
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ICS1893CK-40 Data Sheet Rev Release 5.1 MII Data Interface The ICS1893CK-40’s MAC Interface is the Media Independent Interface (MII) operating at either 10 Mbps or 100 Mbps. The ICS1893CK-40 MAC Interface is configured for the MII Data Interface ...
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... The transformer provides the isolation with one set of windings on one ground plane and another set of windings on the second ground plane. 5.3.1 Twisted-Pair Transmitter The twisted-pair transmitter driver uses an H-bridge configuration. IDT transformer requirements: • Turns Ratio 1:1 • Chokes may be used on chip or cable side or both sides • ...
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ICS1893CK-40 Data Sheet Rev Release Figure 5-1. ICS1893CK-40 Twisted Pair * TP_AP 12 ICS1893CK TP_AN 13 Ideally, for these traces Z TP_BP 16 TP_BN 15 Ideally, for these traces Z * For backward compatibility, refer to the the ...
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ICS1893CK-40 Data Sheet - Release 5.4 Clock Reference Interface The REF_IN pin provides the ICS1893CK-40 Clock Reference Interface. The ICS1893CK-40 requires a single clock reference with a frequency of 25 MHz ±50 parts per million. This accuracy is necessary to ...
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ICS1893CK-40 Data Sheet Rev Release If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893CK-40. A pair of bypass capacitors on either side ...
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ICS1893CK-40 Data Sheet - Release 5.5 Status Interface The ICS1893CK-40 provides five multi-function configuration pins that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table 8.6.) Table ...
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ICS1893CK-40 Data Sheet Rev Release Figure 5-3 shows typical biasing and LED connections for the ICS1893CK-40. Figure 5-3. ICS1893CK-40 LED - PHY Interface P4RD P3TD 8 6 REC 10KΩ 10KΩ This circuit decodes to PHY address = 1. ...
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ICS1893CK-40 Data Sheet - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893CK-40 functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA ...
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ICS1893CK-40 Data Sheet Rev Release 6.1 Functional Block: Media Independent Interface All ICS1893CK-40 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893CK-40 MIIs can support two data transfer rates: 25 MHz (for ...
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ICS1893CK-40 Data Sheet - Release 6.2 Functional Block: Auto-Negotiation The auto-negotiation logic of the ICS1893CK-40 has the following main functions: • To determine the capabilities of the remote link partner, (that is, the device at the other end of the ...
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ICS1893CK-40 Data Sheet Rev Release 6. To indicate that the auto-negotiation process is complete, the ICS1893CK-40 sets bits 1.5 and 17.4 high to logic one. After successful completion of the auto-negotiation process, the ICS1893CK-40 Auto-Negotiation sublayer performs the ...
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ICS1893CK-40 Data Sheet - Release 6.2.3 Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893CK-40 reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, ...
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ICS1893CK-40 Data Sheet Rev Release 6.2.5 Auto-Negotiation: Progress Monitor Under typical circumstances, the Auto-Negotiation sublayer can establish a connection with the ICS1893CK-40’s remote link partner. However, some situations can prevent the auto-negotiation process from properly achieving this goal. ...
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ICS1893CK-40 Data Sheet - Release 6.3.3 PCS/PMA Transmit Modules Both the PCS and PMA sublayers have Transmit modules. 6.3.3.1 PCS Transmit Module The ICS1893CK-40 PCS Transmit module accepts nibbles from the MAC Interface and converts the nibbles into 5-bit ‘code ...
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ICS1893CK-40 Data Sheet Rev Release Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to the MAC Interface. Detection of an error forces the Receive state machine to assert ...
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ICS1893CK-40 Data Sheet - Release 6.3.6 4B/5B Encoding/Decoding The 4B/5B encoding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”). There are 32 five-bit symbols, which include the following: • Of the 32 five-bit symbols, ...
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ICS1893CK-40 Data Sheet Rev Release 6.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder When operating in the 100Base-TX mode, the ICS1893CK-40 TP-PMD sublayer employs an MLT-3 encoder and decoder. During data transmission, the TP-PMD encoder converts the NRZI bit stream received ...
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... The 10Base-T and 100Base-TX operations differ as follows. 10Base-T operations are fundamentally simpler than 100Base-TX operations. The data rate is slower, requiring less encoding than 100Base-TX operations. In addition, the bandwidth requirements (and therefore the line attenuation issues) are not as severe as with 100-MHz operations. Consequently, when an ICS1893CK-40 is set for 10Base-T operations, it requires fewer internal circuits in contrast to 100Base-TX operations ...
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ICS1893CK-40 Data Sheet Rev Release During 10Base-T data reception, a Manchester Decoder translates the serial bit stream obtained from the Twisted-Pair Receiver (MDI) into an NRZ bit stream. The Manchester Decoder then passes the data to the MAC ...
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ICS1893CK-40 Data Sheet - Release When the 10Base-T link is: • Invalid, and the Smart Squelch function is: – Disabled (bit 18.0 is logic one), the Link Monitor Function must detect at least one of the following events before transitioning ...
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ICS1893CK-40 Data Sheet Rev Release 6.5.7 10Base-T Operation: Carrier Detection The ICS1893CK-40 has a 10Base-T Carrier Detection Function that establishes the state of its Carrier Sense signal (CRS), based upon the state of its Transmit and Receive state ...
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ICS1893CK-40 Data Sheet - Release An ICS1893CK-40 SQE Test Function is: • Enabled only when all the following conditions are true: – The ICS1893CK- node mode. – The ICS1893CK- half-duplex mode. – The ICS1893CK-40 has a ...
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ICS1893CK-40 Data Sheet Rev Release When an ICS1893CK-40 detects a reversed signal polarity on its Twisted-Pair Receiver pins and the Auto Polarity-Inhibit bit is also logic zero (enabled), the ICS1893CK-40 (1) automatically corrects the data stream and (2) ...
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ICS1893CK-40 Data Sheet - Release Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE periods are not part of the Management Frame Structure. Table 6-1. Management Frame Structure Summary Frame Field Acronym Frame ...
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... Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893CK-40 and the STA. All Management Registers are 16 bits wide, matching the width of the Data field. During a transaction that is a: • Read, (OP is 10b) the ICS1893CK-40 obtains the contents of the register identified in the REGAD field and returns this Data to the STA synchronously with its MDC signal. • ...
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ICS1893CK-40 Data Sheet - Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (IDT) Registers Table 7-2 lists the IDT-specific registers that the ICS1893CK-40 implements. These registers enhance the performance of the ICS1893CK-40 and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. IDT-Specific Registers Register Address ...
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ICS1893CK-40 Data Sheet - Release 7.1.2 Management Register Bit Access The ICS1893CK-40 Management Registers include one or more of the following types of bits: Table 7-3. Description of Management Register Bit Types Management Register Bit Types Symbol Read-Only Command Override ...
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ICS1893CK-40 Data Sheet Rev Release 7.1.4 Management Register Bit Special Functions This section discusses the types of special functions for the Management Register bits. 7.1.4.1 Latching High Bits The purpose of a latching high (LH) bit is to ...
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ICS1893CK-40 Data Sheet - Release 7.2 Register 0: Control Register Table 7-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes of the ICS1893CK-40. • The Control Register is accessible through the ...
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ICS1893CK-40 Data Sheet Rev Release 7.2.2 Loopback Enable (bit 0.14) This bit controls the Loopback mode for the ICS1893CK-40. Setting this bit to logic: • Zero disables the Loopback mode. • One enables the Loopback mode by disabling ...
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ICS1893CK-40 Data Sheet - Release 7.2.5 Low Power Mode (bit 0.11) This bit provides one way to control the ICS1893CK-40 low-power mode function. When bit 0.11 is logic: • Zero, there is no impact to ICS1893CK-40 operations. • One, the ...
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ICS1893CK-40 Data Sheet Rev Release 7.2.8 Duplex Mode (bit 0.8) This bit provides a means of controlling the ICS1893CK-40 Duplex Mode. • The function of bit 0.8 depends on the Auto-Negotiation Enable bit, 0.12. When the auto-negotiation process ...
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ICS1893CK-40 Data Sheet - Release 7.3 Register 1: Status Register Table 7-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893CK-40 and an STA. There are two types of status bits: some report ...
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ICS1893CK-40 Data Sheet Rev Release 7.3.2 100Base-TX Full Duplex (bit 1.14) The STA reads this bit to learn if the ICS1893CK-40 can support 100Base-TX, full-duplex operations. The ISO/IEC specification requires that the ICS1893CK-40 must set bit 1.14 to ...
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ICS1893CK-40 Data Sheet - Release 7.3.6 IEEE Reserved Bits (bits 1.10:7) The IEEE reserves these bits for future use. When an STA: • Reads a reserved bit, the ICS1893CK-40 returns a logic zero. • Writes a reserved bit, the STA ...
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ICS1893CK-40 Data Sheet Rev Release 7.3.9 Remote Fault (bit 1.4) An STA reads bit 1.4 to determine if a Remote Fault exists. The ICS1893CK-40 sets bit 1.4 based on the Remote Fault bit received from its remote link ...
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ICS1893CK-40 Data Sheet - Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893CK-40 detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893CK-40 Jabber Detection function is ...
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ICS1893CK-40 Data Sheet Rev Release 7.4 Register 2: PHY Identifier Register Table 7-7 lists the bits for PHY Identifier Register (Register 2), which is one of two PHY Identifier Registers that are part of a set defined by ...
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ICS1893CK-40 Data Sheet - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. This OUI is retained for backwards compatibility with older ...
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... Bits 3.3:0 2 0000 ICS1893CK-40, Rev. C, 06/02/09 When Bit = 0 When Bit = 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Description IDT 1893C Copyright © 2009, Integrated Device Technology, Inc. All rights reserved. 57 Chapter 7 Management Register Set Access Special Default Hex Function CW – – – – – – – ...
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ICS1893CK-40 Data Sheet - Release 7.6 Register 4: Auto-Negotiation Register Table 7-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the ICS1893CK-40 capabilities that it wants to advertise to its remote link partner. During ...
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ICS1893CK-40 Data Sheet Rev Release 7.6.2 IEEE Reserved Bit (bit 4.14) The ISO/IEC specification reserves this bit for future use. However, the ISO/IEC Standard also defines bit 4.14 as the Acknowledge bit. When this reserved bit is read ...
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ICS1893CK-40 Data Sheet - Release 7.6.5 Technology Ability Field (bits 4.9:5) When its Auto-Negotiation sublayer is enabled, the ICS1893CK-40 transmits its link capabilities to its remote link partner during the auto-negotiation process. The Technology Ability Field (TAF) bits 4.12:5 determine ...
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ICS1893CK-40 Data Sheet Rev Release auto-negotiation process. The ICS1893CK-40 supports IEEE Std. 802.3, represented by a value of 00001b in bits 4.4:0. The ISO/IEC 8802-3 standard defines the Selector Field technologies in Annex 28A. ICS1893CK-40, Rev. C, 06/02/09 ...
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ICS1893CK-40 Data Sheet - Release 7.7 Register 5: Auto-Negotiation Link Partner Ability Register Table 7-12 lists the bits for the Auto-Negotiation Link Partner Ability Register. An STA uses this register to determine the capabilities being advertised by the remote link ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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ICS1893CK-40 Data Sheet Rev Release 7.8.2 Parallel Detection Fault (bit 6.4) The ICS1893CK-40 sets this bit to a logic one if a parallel detection fault is encountered. A parallel detection fault occurs when the ICS1893CK-40 cannot disseminate the ...
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ICS1893CK-40 Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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ICS1893CK-40 Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word ...
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... Written STA, the STA must use the default value specified in this data sheet. IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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ICS1893CK-40 Data Sheet - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893CK-40 provides to allow an STA to customize the operations of the device. Note: 1. For an ...
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... To alter additional CW bits, the Command Override Write Enable bit must once again be set to logic one. 7.11.2 ICS Reserved (bits 16.14:11) IDT is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits. When one of these reserved bits is: • ...
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ICS1893CK-40 Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893CK-40 to transmit symbols that are typically classified as invalid. The purpose of this test bit ...
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ICS1893CK-40 Data Sheet Rev Release 7.12 Register 17: Quick Poll Detailed Status Register Table 7-18 lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only register used to provide an STA with detailed ...
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ICS1893CK-40 Data Sheet - Release 7.12.1 Data Rate (bit 17.15) • The value of this bit is determined by the Data Rate bit 0.13. When bit 17.15 is logic: • Zero, it indicates that 10-MHz operations are selected. • One, ...
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ICS1893CK-40 Data Sheet Rev Release Table 7-19. Auto-Negotiation State Machine (Progress Monitor) Auto-Negotiation State Machine Consistency Match Failure Consistency Matched Auto-Negotiation Completed Successfully 7.12.4 100Base-TX Receive Signal Lost (bit 17.10) The 100Base-TX Receive Signal Lost bit indicates to ...
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ICS1893CK-40 Data Sheet - Release 7.12.6 False Carrier (bit 17.8) The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893CK-40 in 100Base mode. A False Carrier occurs when the ICS1893CK-40 begins evaluating potential ...
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ICS1893CK-40 Data Sheet Rev Release 7.12.9 Premature End (bit 17.5) The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893CK-40. During reception of a valid packet, ...
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ICS1893CK-40 Data Sheet - Release 7.13 Register 18: 10Base-T Operations Register The 10Base-T Operations Register provides an STA with the ability to monitor and control the ICS1893CK-40 activity while the ICS1893CK-40 is operating in 10Base-T mode. Note: 1. For an ...
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ICS1893CK-40 Data Sheet Rev Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893CK-40 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. ...
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ICS1893CK-40 Data Sheet - Release 2. This bit is a control bit and not a status bit. Therefore not updated to indicate this automatic inhibiting of the SQE test in full-duplex mode or repeater mode. 7.13.8 Link Loss ...
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ICS1893CK-40 Data Sheet Rev Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893CK-40 operations. Note: 1. For an explanation of acronyms used in 2. During any write ...
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ICS1893CK-40 Data Sheet - Release 7.14.1 Node Configuration (bit 19.15) The Node Configuration bit indicates the NOD/MODE. • In Node mode: – The SQE Test default setting is enabled. – The Carrier Sense signal (CRS) is asserted in response to ...
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ICS1893CK-40 Data Sheet Rev Release cross transmit = TP_BP & TP_BN receive = TP_AP & TP_AN AMDIX_EN [19:9] MDI_MODE [19:8] MDIO register 13h bit 8 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893CK-40 provides a Twisted ...
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ICS1893CK-40 Data Sheet - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893CK-40 Pin Diagram P4RD TP_AP TP_AN VDD TP_BN TP_BP VSS AVDD 10TCSR 100TCSR 8.2 ICS1893CK-40 Pin Descriptions Table 8-1. ICS1893CK-40 MAC Interface Pins Signal Name MDIO MDC ...
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ICS1893CK-40 Data Sheet Rev Release Table 8-1. ICS1893CK-40 MAC Interface Pins Signal Name RXD0 RXDV RXCLK RXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3 Table 8-2. ICS 1893CF Multifunction Pins: PHY Address and LED Pins Signal Name P4RD P3TD ...
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ICS1893CK-40 Data Sheet - Release 8.2.1 Transformer Interface Pins Transformer connections on the ICS1893CK-40 signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8.4. The previous TP_CT pin on the ICS1893AF is not used with the ICS1893CK-40. The typical ...
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ICS1893CK-40 Data Sheet Rev Release Note: Each of these pins monitor the data link by providing signals that directly drive LEDs. Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P0AC 36 Input or ...
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ICS1893CK-40 Data Sheet - Release Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P2LI 38 Input or Output P3TD 39 Input or Output ICS1893CK-40, Rev. C, 06/02/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin ...
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ICS1893CK-40 Data Sheet Rev Release Table 8-5. PHY Address and LED Pins Pin Pin Pin Name Number Type P4RD 1 Input or Output ICS1893CK-40, Rev. C, 06/02/09 Chapter 8 Pin Diagram, Listings, and Descriptions Pin Description PHY (Address ...
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ICS1893CK-40 Data Sheet - Release 8.2.3 Configuration Pins Table 8-6 lists the configuration pins. Table 8-6. Configuration Pins Pin Pin Name Number 10TCSR 9 Output 100TCSR 10 Output REF_IN 34 REF_OUT 33 Output RESETn 13 ICS1893CK-40, Rev. C, 06/02/09 Chapter ...
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ICS1893CK-40 Data Sheet Rev Release 8.2.4 MAC Interface Pins This section lists pin descriptions for each of the following interfaces • Section 8.2.4.1, “MAC Interface Pins for Media Independent Interface” 8.2.4.1 MAC Interface Pins for Media Independent Interface ...
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ICS1893CK-40 Data Sheet - Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXCLK 23 Output RXD0 21 Output RXD1 20 RXD2 19 RXD3 18 RXDV 22 Output ICS1893CK-40, Rev. C, 06/02/09 ...
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ICS1893CK-40 Data Sheet Rev Release Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued) Pin Pin Pin Name Number Type RXER 24 Output TXCLK 26 Output TXD0 28 Input TXD1 29 TXD2 30 TXD3 31 TXEN 27 ...
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ICS1893CK-40 Data Sheet - Release 8.2.5 Ground and Power Pins Table 8-8. Ground and Power Pins Signal Name VDD VDD VDD VDD VDD AVDD VDDIO VSS VSS AVSS VSSIO ICS1893CK-40, Rev. C, 06/02/09 Chapter 8 Pin Diagram, Listings, and Descriptions ...
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... Table 9-1 lists absolute maximum ratings. Stresses above these ratings can permanently damage the ICS1893CK-40. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the ICS1893CK-40 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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ICS1893CK-40 Data Sheet - Release 9.3 Recommended Component Values * Table 9-3. Recommended Component Values for ICS1893CK-40 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std. 802.3 requirements that define the ...
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ICS1893CK-40 Data Sheet Rev Release 9.4 DC Operating Characteristics This section lists the ICS1893CK-40 DC operating characteristics. 9.4.1 DC Operating Characteristics for Supply Current Table 9-4 lists the DC operating characteristics for the supply current to the ICS1893CK-40 ...
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ICS1893CK-40 Data Sheet - Release 9.4.3 DC Operating Characteristics for REF_IN Table 9-6 lists the 3.3-V DC characteristics for the REF_IN pin. Note: The REF_IN input switch point is 50% of VDD. Table 9-6. 3.3-V DC Operating Characteristics for REF_IN ...
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ICS1893CK-40 Data Sheet Rev Release 9.5 Timing Diagrams 9.5.1 Timing for Clock Reference In (REF_IN) Pin Table 9-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. shows the timing diagram for the ...
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ICS1893CK-40 Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.3 Timing for Receive Clock (RXCLK) Pins Table 9-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various interfaces. Figure 9-4 shows the timing diagram for ...
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ICS1893CK-40 Data Sheet - Release 9.5.4 100M MII: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.5 10M MII: Synchronous Transmit Timing Table 9-12 lists the significant time periods for the 10M MII synchronous transmit timing. The time periods consist of timings of signals on the following pins: • ...
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ICS1893CK-40 Data Sheet - Release 9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.7 MII Management Interface Timing Table 9-14 lists the significant time periods for the MII Management Interface timing (which consists of timings of signals on the MDC and MDIO pins). Table 9-14. MII ...
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ICS1893CK-40 Data Sheet - Release 9.5.8 10M Media Independent Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M MII timing. The time periods consist of timings of signals on the following pins: • TP_RX (that is, ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.9 10M Media Independent Interface: Transmit Latency Table 9-16 lists the significant time periods for the 10M MII transmit latency. The time periods consist of timings of signals on the following pins: • ...
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ICS1893CK-40 Data Sheet - Release 9.5.10 100M / MII Media Independent Interface: Transmit Latency Table 9-17 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the ...
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ICS1893CK-40 Data Sheet - Release 9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-19 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.13 100M MII Media Independent Interface: Receive Latency Table 9-20 lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The time periods consist of timings of signals ...
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ICS1893CK-40 Data Sheet - Release 9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-21 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.15 Reset: Power-On Reset Table 9-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 9-16 ...
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... Table 9-23. Hardware Reset and Power-Down Timing Time Period t1 RESETn Active to Device Isolation and Initialization t2 Minimum RESETn Pulse Width t3 RESETn Released to TXCLK Valid Figure 9-17. Hardware Reset and Power-Down Timing Diagram REF_IN RESETn TXCLK Valid ...
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ICS1893CK-40 Data Sheet Rev Release 9.5.17 10Base-T: Heartbeat Timing (SQE) Table 9-24 lists the significant time periods for the 10Base-T heartbeat (that is, the Signal Quality Error). The time periods consist of timings of signals on the following ...
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ICS1893CK-40 Data Sheet - Release 9.5.18 10Base-T: Jabber Timing Table 9-25 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and ...
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... Normal Link Pulse (which consists of timings of signals on the TP_TXP pins). Table 9-26. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 9-20. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893CK-40, Rev. C, 06/02/09 Figure 9-20 shows the timing diagram for the time periods ...
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... Period t1 Clock/Data Pulse Width t2 Clock Pulse-to-Data Pulse Timing t3 Clock Pulse-to-Clock Pulse Timing t4 Fast Link Pulse Burst Width t5 Fast Link Pulse Burst to Fast Link Pulse Burst t6 Number of Clock/Data Pulses in a Burst Figure 9-21. Auto-Negotiation Fast Link Pulse Timing Diagram Clock Pulse ...
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ICS1893CK-40 Data Sheet Rev Release Chapter 10 Package Outline and Package Dimensions (40-pin, 6mm x 6mm MLF ) Package dimensions are kept current with JEDEC Publication No. 95 Seating Plane Index Area Top View ...
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ICS1893CK-40 Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. shows ordering information for the ICS1893CK-40. Part / Order Number 1893CKI-40LF 1893CKI40LF 40-Lead MLF Lead/Pb-Free 1893CKI-40LFT 1893CKI40LF 40-Lead MLF Lead/Pb-Free, Tape and Reel ICS1893CK-40, Rev. C, 06/02/09 Marking Package ...
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... ICS1893CK-40 Data Sheet Rev Release Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com ICS1893CK-40, Rev. C, 06/02/09 For Tech Support 408-284-4522 www.idt.com/go/clockhelp Copyright © 2009, Integrated Device Technology, Inc. ...