1893CKLFT IDT, 1893CKLFT Datasheet - Page 77

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

7.12.9 Premature End (bit 17.5)
7.12.10 Auto-Negotiation Complete (bit 17.4)
7.12.11 100Base-TX Signal Detect (bit 17.3)
7.12.12 Jabber Detect (bit 17.2)
7.12.13 Remote Fault (bit 17.1)
7.12.14 Link Status (bit 17.0)
ICS1893CK-40, Rev. C, 06/02/09
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1893CK-40.
During reception of a valid packet, the ICS1893CK-40 examines each symbol to ensure that the data being
passed to the MAC Interface is error free. If two consecutive Idles are encountered, it indicates this
condition to the MAC by setting this bit.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
Note:
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
•
•
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
•
•
Bit 17.2 is functionally identical to bit 1.1. The Jabber Detect bit indicates whether a jabber condition has
occurred. This bit is a 10Base-T function.
Bit 17.1 is functionally identical to bit 1.4.
Bit 17.0 is functionally identical to bit 1.2.
Zero, it indicates a Premature End condition has not been detected since either the last read or reset of
this register.
One, it indicates a Premature End condition was detected in the packet since either the last read or reset
of this register.
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1893CK-40 has completed the auto-negotiation process and that the
contents of Management Registers 4, 5, and 6 are valid.
Zero when no signal is detected on the Twisted-Pair Receive pins.
One when a signal is present on the Twisted-Pair Receive pins.
This bit has no definition in 10Base-T mode.
ICS1893CK-40 Data Sheet Rev. C - Release
and
Copyright © 2009, Integrated Device Technology, Inc.
Section 7.1.4.2, “Latching Low
All rights reserved.
77
Bits”.)
Chapter 7 Management Register Set
Section
June 2009