1893CKLFT IDT, 1893CKLFT Datasheet - Page 39

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

6.5.14 10Base-T Operation: Isolation Transformer
6.6 Functional Block: Management Interface
6.6.1 Management Register Set Summary
6.6.2 Management Frame Structure
ICS1893CK-40, Rev. C, 06/02/09
When an ICS1893CK-40 detects a reversed signal polarity on its Twisted-Pair Receiver pins and the Auto
Polarity-Inhibit bit is also logic zero (enabled), the ICS1893CK-40 (1) automatically corrects the data
stream and (2) sets its Polarity Reversed bit (bit 18.14) to logic one, to indicate to the STA that this situation
exists. Bit 18.14 is a latching high (LH) bit. (For more information on latching high and latching low bits, see
Section 7.1.4.1, “Latching High Bits”
Note:
The 10Base-T Isolation Transformer operates the same as the 100Base-TX Isolation Transformer. In fact,
in a typical ICS1893CK-40 application they are the same unit. For more information, see
“100Base-TX Operation: Isolation
As part of the MAC Interface, the ICS1893CK-40 provides a two-wire serial management interface which
complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to
exchange control, status, and configuration information between a Station Management entity (STA) and
the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of
management registers. The ISO/IEC standard specifies the following components of this serial
management interface:
•
•
•
In compliance with the ISO/IEC specification, the ICS1893CK-40 implementation of the serial management
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the
exchange of data. These pins remain active in all ICS1893CK-40 MAC Interface modes (that is, the 10/100
MII, 100M Symbol, and 10M Serial interface modes).
The ICS1893CK-40 implements a Management Register set that adheres to the ISO/IEC standard. This
register set (discussed in detail in
Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the
exchange of configuration, control, and status data between a PHY, such as an ICS1893CK-40, and an
STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA
exchange data through a pre-defined register set.
The ICS1893CK-40 complies with the ISO/IEC defined Management Frame Structure and protocol. This
structure supports both read and write operations.
Structure.
A set of registers
The frame structure
The protocol
The ICS1893CK-40 will not complete the Auto-MDIX function for an inverted polarity cable.
This is a rare event with modern manufactured cables. Full Auto-Negotiation and Auto
Polarity Correction will complete when the Auto-MDIX function is disabled. Software control
for the Auto-MDIX function is available in MDIO Register 19 Bits 9:8.
ICS1893CK-40 Data Sheet Rev. C - Release
(Section 6.6.1, “Management Register Set
(Section 6.6.2, “Management Frame
Copyright © 2009, Integrated Device Technology, Inc.
Chapter 7, “Management Register
Transformer”.
and
Section 7.1.4.2, “Latching Low
All rights reserved.
39
Table 6-1
Structure”)
summarizes the Management Frame
Summary”)
Set”) includes the mandatory ‘Basic’
Bits”.)
Chapter 6 Functional Blocks
Section 6.4.7,
June 2009