78Q2123/F1 Maxim Integrated, 78Q2123/F1 Datasheet - Page 12

• Manufacturer Part Number: 78Q2123/F1
• Description: Ethernet ICs
• Manufacturer: Maxim Integrated

Specifications of 78Q2123/F1

• Rohs: yes

78Q2123/78Q2133 Data Sheet
2.3
2.4
2.5
2.6
12
RXD[3:0]
RX_ER
MDC
MDIO
Signal
Signal
Signal
Signal
RST
INTR
TXOP,
TXON
RXIP,
RXIN
XTLP
XTLN
PWR
GND
MDI (Media Dependent Interface)
Oscillator/Clock
Power Supply and Ground
Control and Status
Pin
Pin
Pin
Pin
10, 29
30,31
28,27
9, 26
[5:8]
24
25
23
32
13
2
1
Type
Type
Type
Type
COZ
COZ
COZ
CIO
CIS
CIS
A
A
A
A
S
G
RECEIVE DATA: Received data is provided to the MAC via RXD[3:0].
These pins are tri-stated in isolate mode.
RECEIVE ERROR: RX_ER is asserted high when an error is detected
during frame reception. In PCS bypass mode, this pin becomes the MSB of
the receive 5-bit code group. This pin is tri-stated in isolate mode.
MANAGEMENT DATA CLOCK: MDC is the clock used for transferring
data via the MDIO pin.
MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port
used to access management registers within the 78Q2123/78Q2133. This
pin requires an external pull-up resistor as specified in IEEE-802.3.
Description
Description
Description
Description
ACTIVE LOW RESET: When pulled low the pin resets the chip. The reset
pulse must be long enough to guarantee stabilization of the supply
voltage and startup of the oscillator. Refer to the Electrical Specifications
for the reset pulse requirements. There are two other ways to reset the
chip:
INTERRUPT PIN: This pin is used to signal an interrupt to the media
access controller. The pin is held in the high impedance state when an
interrupt is not indicated. The pin will be forced high or low to signal an
interrupt depending upon the value of the INPOL bit (MR16.14). The
events which trigger an interrupt can be programmed via the Interrupt
Control Register located at address MR17.
TRANSMIT OUTPUT POSITIVE/NEGATIVE: Transmitter differential
outputs for both 10base-T and 100base-TX.
RECEIVE INPUT POSITIVE/NEGATIVE: Receiver differential inputs for
both 10BASE-T and 100BASE-TX.
CRYSTAL INPUT: Should be connected to a 25 MHz crystal. If an
externally generated TTL compatibility clock signal is used, that signal is
applied here.
CRYSTAL OUTPUT: Should be connected to a 25 MHz crystal. When an
external clock source is being used, this pin must be grounded.
+3.3VDC SUPPLY
GROUND
1. Through the internal power-on-reset (activated when the chip is
2. Through the MII register bit (MR 0.15).
being powered up).
DS_21x3_001
Rev. 1.6