IS25CQ032-JKLE-TR ISSI, IS25CQ032-JKLE-TR Datasheet - Page 35

• Manufacturer Part Number: IS25CQ032-JKLE-TR
• Description: Flash 32M, 2.7-3.6V 104Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25CQ032-JKLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: WSON-8
• Organization: 4096 K x 8

DEVICE OPERATION (CONTINUED)
Program Security information Row instruction (PSIR)
The PSIR instructions can read and programmed (Erase) using three dedicated instructions. The program
information Raw instruction is used to program at most 65 bytes to the security memory area (by changing bits
from ‘1’ to ‘0’, only). Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded, the device sets the write enable latch
(WEL) bit. The program information Row instruction is entered by driving CE# pin Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (SI). CE# pin must be
driven High after the eighth bits of the last data byte has been latched in, otherwise the Program information
Row instruction is not executed. If more than 64 bytes data are sent to a device, the address counter can not roll
over.
program OTP cycle is in progress, the status register may be read to check the value of the write in progress
(WIP) bit. The write in progress (WIP) bit is 1 during the self-timed program cycle, and it is 0 when it is
completed. At some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.
Note: 1  n  65
Note: 1. The SIR address is from 000000h to 00003Fh.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
2/1/2013
After CE# pin is driven High, the self-timed page program cycle (whose duration is t
SCK
CE#
2. The SIR protection bit is in the address 000040h
SCK
CE#
SI
SI
Figure 30. Program information Raw Sequence
MSB
7
32
0
INSTRUCTION = 1011 0001b
6
33
1
Data Byte 1
5
34
2
4
35
3
3
36
4
2
37
5
1
38
6
0
39
7
MSB
23
8
40
7
Data Byte 2
22
41
9
6
10
21
42
24-bit address
5
11
43
...
...
...
...
28
IS25CQ032
potp
) is initiated. While the
29
2
Data Byte n
30
1
31
0
35