GLS55VD020-60-C-TQWE-DZ019 Greenliant, GLS55VD020-60-C-TQWE-DZ019 Datasheet - Page 8

• Manufacturer Part Number: GLS55VD020-60-C-TQWE-DZ019
• Description: Flash ATA Media 60MHz 2.7V Commercial
• Manufacturer: Greenliant

Specifications of GLS55VD020-60-C-TQWE-DZ019

• Rohs: yes
• Memory Type: NAND Flash
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100

Data Sheet
TABLE 1: P
©2010 Greenliant Systems, Ltd.
Symbol
IORD#
HDMARDY#
HSTROBE
IOWR#
STOP
IOCS16#
INTRQ
PDIAG#
DASP#
RESET#
WP#/PD#
Flash Media Interface
FRE#
FWE#
FCLE
FALE
FAD15
FAD14
FAD13
FAD12
FAD11
FAD10
FAD9
FAD8
IN
A
TQFP
SSIGNMENTS
100-
19
57
55
21
54
75
97
84
96
92
94
46
44
42
40
35
33
31
29
1
Pin No.
VFBGA
D10
K10
85-
D1
C2
C1
H2
H7
H3
H6
C5
C7
E9
K6
A3
B4
A5
A7
B8
B9
J7
(C
ONTINUED
Type
Pin
I/O
I/O
I/O
O
O
O
I
I
I
I
) (2
I1U/O1
I1U/O6
I3U/O5
Type
I2U
I3U
I2Z
I2Z
O2
O1
I/O
O5
OF
1
4)
Name and Functions
IORD#: This is an I/O Read Strobe generated by the host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device.
HDMARDY#: In Ultra DMA mode when DMA Read is active, this
signal is asserted by the host to indicate that the host is ready to
receive Ultra DMA data-in bursts. The host may negate
HDMARDY# to pause an Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out
strobe generated by the host. Both the rising and falling edges of
HSTROBE cause data to be latched by the device. The host may
stop generating HSTROBE edges to pause an Ultra DMA data-out
burst.
This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into
the device.
When Ultra DMA mode protocol is active, the assertion of this sig-
nal causes the termination of the Ultra DMA burst
This output signal is asserted low when the device is indicating a
word data transfer cycle.
This signal is the active high Interrupt Request to the host.
The Pass Diagnostic signal in the Master/Slave handshake proto-
col.
The Drive Active/Slave Present signal in the Master/Slave hand-
shake protocol.
This input pin is the active low hardware reset from the host.
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The
Write Protect or Power-down modes can be selected through the
host command. The Write Protect mode is the factory default set-
ting.
Active Low Flash Media Chip Read
Active Low Flash Media Chip Write
Active High Flash Media Chip Command Latch Enable
Active High Flash Media Chip Address Latch Enable
Flash Media Chip High Byte Address/Data Bus pins
8
This pin accepts only in the 3.3V
NAND Controller
V
DD
signal level.
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