73S8010C-IMR/F1 Maxim Integrated, 73S8010C-IMR/F1 Datasheet - Page 7

• Manufacturer Part Number: 73S8010C-IMR/F1
• Description: I2C Interface IC
• Manufacturer: Maxim Integrated

Specifications of 73S8010C-IMR/F1

• Rohs: yes

2 Host Interface (I
A fast-mode 400 kHz I
the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1,
and SAD2. This allows up to 8 devices to be connected in parallel.
Bit 0 of the I
2.1 Host Interface Control
I
The I
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts
sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’
Rev. 1.5
Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00).
2
Name
Start/Stop
Warm reset
5 V and 3 V
Clock Stop
Clock Stop
Level
Clksel1
Clksel2
I/O enable
C-bus Write to the Control Register
2
C-bus Write command to the control register follows the format shown in
2
C address is the R/W bit. Refer to
Bit
0
1
2
3
4
5
6
7
2
C bus slave interface is used for controlling the device and reading the status of
Description
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence.
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
When set, V
When set, card clock is stopped. Bit 4 determines the card clock stop level.
When set, card clock stops high; when reset card clock stops low.
Bits 5 and 6 determine the clock rate to the card according to the following table.
When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are
high impedance.
SAD2
2
C Bus)
0
0
0
0
1
1
1
1
Table 1: Device Address Selections
CC
Table 2: Host Control Register
SAD1
= 3 V; when reset, V
0
0
1
1
0
0
1
1
CLKDIV1
0
0
1
1
SAD0
Figure 2
0
1
0
1
0
1
0
1
CLKDIV2
and
I
2
C Address (7 bits)
CC
0
1
1
0
Figure 3
= 5 V.
0x4A
0x4C
0x4E
0x40
0x42
0x44
0x46
0x48
for usage.
Clock Rate
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
Figure 2.
7