89HPES8T5ZHBCG IDT, 89HPES8T5ZHBCG Datasheet
89HPES8T5ZHBCG
Specifications of 89HPES8T5ZHBCG
Related parts for 89HPES8T5ZHBCG
89HPES8T5ZHBCG Summary of contents
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... Data Link Layer Mux / Demux Phy Logical Layer SerDes (Port 0) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. © 2008 Integrated Device Technology, Inc. 8-Lane 5-Port PCI Express® Switch ◆ Legacy Support – PCI compatible INTx emulation – ...
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... It provides connectivity for ports across 8 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. The PES8T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac- tion layers ...
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... IDT 89HPES8T5 Data Sheet SMBus Interface The PES8T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES8T5, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES8T5 to be overridden following a reset with values programmed in an external serial EEPROM ...
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... IDT 89HPES8T5 Data Sheet Processor SMBus PES8T5 SSMBCLK SSMBDAT MSMBCLK MSMBDAT (a) Unified Configuration and Management Bus Hot-Plug Interface The PES8T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES8T5 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when- ever the state of a Hot-Plug output needs to be modified, the PES8T5 generates an SMBus transaction to the I/O expander with the new value of all of the outputs ...
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... IDT 89HPES8T5 Data Sheet Signal PE4RP[0] PE4RN[0] PE4TP[0] PE4TN[0] PE5RP[0] PE5RN[0] PE5TP[0] PE5TN[0] PEREFCLKP[2:1] PEREFCLKN[2:1] REFCLKM Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Type Name/Description I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for port 4. O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pair for port 4 ...
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... IDT 89HPES8T5 Data Sheet Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] Type Name/Description I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 I/O General Purpose I/O ...
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... IDT 89HPES8T5 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. ...
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... IDT 89HPES8T5 Data Sheet Signal V CORE APE Type Name/Description I Core VDD. Power supply for core logic. I I/O VDD. LVTTL I/O buffer power supply. I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. ...
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... IDT 89HPES8T5 Data Sheet Pin Characteristics Note: Some input pads of the PES8T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption ...
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... IDT 89HPES8T5 Data Sheet Function System Pins CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT SWMODE[3:0] EJTAG / JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). ...
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... IDT 89HPES8T5 Data Sheet Logic Diagram — PES8T5 Reference Clocks PCI Express Switch SerDes Input Port 0 PCI Express Switch SerDes Input Port 2 PCI Express Switch SerDes Input Port 3 PCI Express Switch SerDes Input Port 4 PCI Express Switch SerDes Input Port 5 Master ...
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... TX-IDLE-TO-DIFF- DATA T Transmitter data skew between any 2 lanes TX-SKEW PCIe Receive UI Unit Interval T Minimum Receiver Eye Width (jitter tolerance) RX-EYE (with jitter) T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ...
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... Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal GPIO 1 GPIO[10:0] 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. GPIO (synchronous output) GPIO (asynchronous input) ...
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... IDT 89HPES8T5 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI Express Analog Power PCI Express Serial Data Transmit ...
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... IDT 89HPES8T5 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below) ...
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... A(allowed) J(desired 100 C - (2.4W * 9.9W/ A(allowed) An appropriate level of increased air flow and/or a heat sink can be added to achieve this lower ambient temperature. Please contact ssdhelp@idt.com for further assistance. Board Size Any Any θ is and assuming a system with 1m/S airflow, the actual value of T ...
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... IDT 89HPES8T5 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V Differential peak-to-peak output voltage TX-DIFFp-p V De-emphasized differential output voltage TX-DE-RATIO V DC Common mode voltage ...
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... IDT 89HPES8T5 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. ...
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... IDT 89HPES8T5 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES8T5 The following table lists the pin numbers and signal names for the PES8T5 device. Pin Function Alt Pin A1 V B17 B18 SS A3 PE0RP03 CORE PE0TN03 C3 A6 ...
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... IDT 89HPES8T5 Data Sheet Pin Function Alt Pin H11 V K12 SS H12 V CORE K13 DD H13 V K14 SS H14 V IO K15 DD H15 V CORE K16 DD H16 GPIO_07 1 K17 H17 GPIO_06 K18 H18 GPIO_05 L1 J1 PE2RN00 L2 J2 PE2RP00 L3 J3 JTAG_TDI CORE ...
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... IDT 89HPES8T5 Data Sheet Pin Function Alt Pin T15 MSMBSMODE U7 T16 V APE U8 DD T17 T18 V CORE U10 DD U1 PE3TP00 U11 U2 PE3TN00 U12 U13 U14 U15 U16 SS Alternate Signal Functions Function Alt Pin V U17 PE4RN00 U18 ...
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... IDT 89HPES8T5 Data Sheet Power Pins V Core V Core F10 A6 F15 A8 G12 A10 H4 A12 H7 A14 H9 A15 H10 B17 H12 B18 H15 C4 J6 C13 J9 C16 J10 D4 J13 D14 K1 D15 K5 E5 K18 E14 Core L10 B1 L11 B2 L12 ...
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... IDT 89HPES8T5 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 E11 E13 F11 K7 F12 K8 F13 K9 F14 K10 F16 K11 G4 K12 G6 K13 G7 K14 G8 K16 G9 K17 G11 ...
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... IDT 89HPES8T5 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 GPIO_08 GPIO_09 GPIO_10 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE PE0RN00 PE0RN01 PE0RN02 PE0RN03 PE0RP00 PE0RP01 PE0RP02 ...
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... IDT 89HPES8T5 Data Sheet Signal Name PE0TN01 PE0TN02 PE0TN03 PE0TP00 PE0TP01 PE0TP02 PE0TP03 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PE4RN00 PE4RP00 PE4TN00 PE4TP00 PE5RN00 PE5RP00 PE5TN00 PE5TP00 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK ...
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... IDT 89HPES8T5 Data Sheet Signal Name SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location I D17 I D16 I E15 I E16 See Table 21 for a listing of power pins. IO, See Table 22 for a listing of ground pins. Table 23 89PES8T5 Alphabetical Signal List (Part ...
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... IDT 89HPES8T5 Data Sheet PES8T5 Pinout — Top View Core (Power I/O (Power (Power (Power APE (Power) ...
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... IDT 89HPES8T5 Data Sheet PES8T5 Package Drawing — 324-Pin BC324/BCG324 March 27, 2008 ...
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... IDT 89HPES8T5 Data Sheet PES8T5 Package Drawing — Page Two March 27, 2008 ...
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... IDT 89HPES8T5 Data Sheet Revision History February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 27, 2008: In Table 16, Thermal Specifications, added ...
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... A AAA NN Product Operating Device Family Voltage Family Valid Combinations 89HPES8T5ZHBC 324-pin BC324 package, Commercial Temperature 89HPES8T5ZHBCG 324-pin Green BCG324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 ® NNAN AA AA Package Temp Range Product Device Detail ...