89HPES8T5ZHBCG IDT, 89HPES8T5ZHBCG Datasheet - Page 4

• Manufacturer Part Number: 89HPES8T5ZHBCG
• Description: Interface - I/O Expanders
• Manufacturer: IDT

Specifications of 89HPES8T5ZHBCG

• Product Category: Interface - I/O Expanders
• Rohs: yes
• Part # Aliases: IDT89HPES8T5ZHBCG

Hot-Plug Interface
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES8T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES8T5. In response to an I/O expander interrupt, the PES8T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate
functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES8T5 Data Sheet
The PES8T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES8T5 utilizes
The PES8T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
The following tables lists the functions of the pins provided on the PES8T5. Some of the functions listed may be multiplexed onto the same pin. The
Note: In the PES8T5, the 4 downstream ports are labeled ports 2 through 5. There is no port 1.
(a) Unified Configuration and Management Bus
PES8T5
MSMBCLK
SSMBCLK
MSMBDAT
SSMBDAT
PE0RP[3:0]
PE0RN[3:0]
PE0TN[3:0]
PE0TP[3:0]
PE2RP[0]
PE2RN[0]
PE3RP[0]
PE3RN[0]
PE2TP[0]
PE2TN[0]
PE3TP[0]
PE3TN[0]
Signal
Processor
SMBus
Master
Type
O
O
O
I
I
I
EEPROM
Figure 4 SMBus Interface Configuration Examples
Serial
Table 2 PCI Express Interface Pins (Part 1 of 2)
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
...
Devices
SMBus
Other
4 of 31
Name/Description
(b) Split Configuration and Management Buses
PES8T5
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
March 27, 2008