MAX9263GCB/V+T Maxim Integrated, MAX9263GCB/V+T Datasheet - Page 28

• Manufacturer Part Number: MAX9263GCB/V+T
• Description: Serializers & Deserializers - Serdes GMSL Serializer w/HDCP Interface
• Manufacturer: Maxim Integrated

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HDCP Gigabit Multimedia Serial
Link Serializer/Deserializer
The MAX9263/MAX9264 serializer/deserializer chipset
utilizes Maxim’s GMSL technology and HDCP. When
HDCP is enabled, the serializer/deserializer encrypt
video and audio data on the serial link. The serializer/
deserializer are backward compatible with the MAX9259/
MAX9260 serializer/deserializer.
The serializer/deserializer have a maximum serial pay-
load data rate of 2.5Gbps for 15m or more of STP cable.
The serializer/deserializer pair operates up to a maxi-
mum pixel clock of 104MHz for 24-bit mode, or 78MHz
for 32-bit mode, respectively. This serial link supports a
wide range of display panels, from QVGA (320 x 240) to
WXGA (1280 x 800) and higher with 24-bit color.
The 24-bit mode handles 21 bits of high-speed data,
UART control signals, and three audio signals. The 32-bit
mode handles 29 bits of high-speed data, UART control
signals, and three audio signals. The three audio signals
are a standard I
from 8kHz to 192kHz and audio word lengths of 4 bits
to 32 bits. The embedded control channel forms a full-
duplex, differential 9.6kbps to 1Mbps UART link between
the serializer and deserializer for HDCP-related control
operations. In addition, the control channel enables
Table 1. Power-Up Default Register Map (see Tables 22 and 24)
REGISTER
ADDRESS
(hex)
0x00
0x01
0x02
0x03
0x04
POWER-UP DEFAULT
2
0x03, 0x13, 0x83, or
S interface, supporting sample rates
0x1F, 0x3F
Detailed Description
(hex)
0x80
0x90
0x00
0x93
SERID = 1000000, serializer device address is 1000 000
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
DESID = 1001000, deserializer device address is 1001 000
RESERVED = 0
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend
on SSEN pin state at power-up
AUDIOEN = 1, I
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, autocalibrate sawtooth divider
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default
depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
power-up (see the Link Startup Procedure section)
INTTYPE = 00, base mode uses I
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
2
S channel enabled
electronic control unit (ECU), or microcontroller (FC) con-
trol of peripherals in the remote side, such as backlight
control, grayscale gamma correction, camera module,
and touch screen. An ECU/FC, can be located on the
serializer side of the link (typical for video display), on
the deserializer side of the link (typical for image sens-
ing), or on both sides. Base-mode communication with
peripherals uses either I
bypass mode enables full-duplex communication using
a user-defined UART format.
The serializer pre/deemphasis, along with the deseri-
alizer channel equalizer, extends the link length and
enhances the link reliability. Spread spectrum is avail-
able to reduce EMI on the serial and parallel outputs. The
serial link connections comply with ISO 10605 and IEC
61000-4-2 ESD protection standards.
The FC configures various operating conditions of the
serializer and the deserializer through internal registers.
The default device address of the serializer is 0x80
and default device address of the deserializer is 0x90
(Tables 1 and 2). Write to registers 0x00 or 0x01 in both
devices to change the device address of the serializer
or the deserializer.
POWER-UP DEFAULT SETTINGS
2
C
(MSB FIRST)
2
C or the GMSL UART format. A
Register Mapping